[USRP-users] RFNoC -- Making FPGA design easy from GNU Radio

Jacob Gilbert mrjacobagilbert at gmail.com
Mon Dec 8 10:13:07 EST 2014


Matt,

Congratulations on the release of this - this is very exciting! I have a
few questions:

1) This looks targeted at the X3xx series for now; I understand the new
E310 SDR will have RFNoC support also - is there a timeline for this?

2) If I understand the wiki, the current RFNoC FPGA build has a few example
signal processing FPGA blocks (FIR, FFT, window, add/sub) and several
utility blocks (null source/sink, loopback) as well as ‘radio’ blocks. How
does the standard USRP FPGA functionality (DDC/DUC chains, timed commands,
etc) fit into this? Is all of that packaged in the ‘radio’ block or can,
for example, a radio block be programmatically connected to multiple DDC
chains that are independently controlled?

3) What is the FPGA resource utilization of the example X3xx images? Is
there an idea if the same functionality would fit on the E310 FPGA?

Looking forward to where this is going…

Jacob

On Thu, Dec 4, 2014 at 1:52 PM, Matt Ettus via USRP-users <
usrp-users at lists.ettus.com> wrote:

>
> Ettus Research is very excited to announce the release of RFNoC!
>
> Modern FPGAs, like the Xilinx Kintex-7 and ZYNQ used in third generation
> USRPs have incredible computational capability, but taking advantage of
> that capability is difficult at best when using traditional FPGA design
> flows.
>
> RFNoC (which stands for RF Network on Chip) provides the capability to
> create FPGA applications as easily as you create GNU Radio flowgraphs. This
> includes the ability to seamlessly transfer data to & from an FPGA in your
> application, dramatically improving the ease of FPGA off-loading.
>
> Here is an example of an RFNoC flowgraph built using the GNU Radio
> Companion. With four blocks, data is being generated on the host,
> off-loaded to the FPGA for filtering, and then brought back to the host for
> plotting:
>
> [image: Inline image 1]
>
> Signal processing algorithms are encapsulated in easy-to-use wrappers
> which allow them to be dynamically connected and used as needed.  Fixed
> routing is eliminated.  Mixing and matching host-based and FPGA-based
> processing is transparent to the user, and that processing can scale across
> multiple FPGAs and devices across a network.  You can now make custom FPGA
> designs without ever needing to write Verilog or VHDL!
>
> RFNoC has been integrated into UHD for our third generation USRPs
> (X300-series, E300-series, and future devices), enabling you to share FPGA
> designs across devices easily.  Additionally, we have integrated support
> for RFNoC into GNU Radio and GRC, so you can now graphically design mixed
> host- and FPGA-based flowgraphs.
>
>
> Watch an RFNoC presentation and demo from GRCon14:  (long, but HIGHLY
> recommended as an intro)
>
>       https://www.youtube.com/watch?v=9oPxIFtwyb8
>
> All documentation and links to the source code can be found here:
>
>       https://github.com/EttusResearch/uhd/wiki/RFNoC:-Getting-Started
>
> A paper from ACM SIGCOMM with more background:
>
>       http://conferences.sigcomm.org/sigcomm/2013/papers/srif/p45.pdf
>
> If you have any questions, please don't hesitate to ask.  We plan to hold
> most of the RFNoC-related discussion on the usrp-users mailing list.
>
> Matt Ettus
> President, Ettus Research
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users at lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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