[USRP-users] problem about FPGA modification (Min)

Marcus Müller marcus.mueller at ettus.com
Wed Dec 3 03:31:41 EST 2014

Hello Min,

luckily, the N200/N210 comes with a safe boot mode, where it loads
backup images from internal memory.
You have to press a button while powering up, and then your USRP will be
reachable under, under which you can then flash a working
FPGA image; the full procedure is explained in [1].

Best regards,

[1] http://files.ettus.com/manual/page_usrp2.html#usrp2_loadflash_brick
On 12/03/2014 08:30 AM, 天杨 闵 via USRP-users wrote:
> Hello everyone:
> This is Min.I have a big problem right now.I modified the FPGA inside the USRPN200 by modifying the u2plus_core.v fileWhat I did is comment out all the packet_router part like below,then I synthesized the u2plus_core.v and generate programming file u2plus.binthen I rename u2plus.bin into Usrp_n200_r4_fpga.binthen I burned this bin file into FPGA by using usrp_n2xx_net_burner_gui.pyHowever, when I tried to use uhf_fft, I found the usrp can not be connected to PCanymore, also when I try to reburn the FPGA with original bin file, I founder the burner can not be connected to USRP anymore.What should I do, please help me
> Thanks in advance
> Min
> //   packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router//     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),//      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),//      .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),////      .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),////      .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0),////      .status(status), .sys_int_o(buffer_int), .debug(router_debug),////      .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o),//      .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o),//      .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o),//      .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),//      .err_inp_data(tx_err_data), .err_inp_valid(tx_err_src_rdy), .err_inp_ready(tx_err_dst_rdy),//      .ctl_inp_data(sfc_wr_data), .ctl_inp_valid(sfc_wr_valid),   .ctl_inp_ready(sfc_wr_ready),////      .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i),//      .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),//      .ctl_out_data(sfc_rd_data), .ctl_out_valid(sfc_rd_valid), .ctl_out_ready(sfc_rd_ready),//      .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)//      );
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