[USRP-users] Direct Programming the FPGA

Eddie Carle eddie at isatec.ca
Mon Dec 1 23:18:52 EST 2014

On Mon, 2014-12-01 at 10:45 -0800, Ian Buckley wrote:
> Eddie, 
> You are right to be concerned about the amount of work involved in
> building an X300 image from scratch. Some of the interfaced logic
> use's high speed interfaces and/or has tricky programming and there's
> been a vast amount of man hours spent on getting that all working
> well. All the HDL code is published here:
> https://github.com/EttusResearch/fpga/tree/master look under the usrp3
> directory for X300 related code. Most X300 peripheral programming is
> actually done on the host from the UHD code base, just the actual
> SPI/I2C controllers etc are on the X300.
> In most cases such as your own it's possible to do a little creative
> hacking and insert your custom HDL into the Ettus HDL and then
> piggyback on all the work already done in UHD.
> There is also a new Ettus methodology to customize the X300 HDL called
> RFNoC which might work for
> you: https://github.com/EttusResearch/uhd/wiki/RFNoC:-Getting-Started
> I have built entirely custom FPGA designs for older USRP's such as the
> N210 which are simpler system designs and that might be another
> approach to consider if you don't need the full X300
> performance/capacity. However older USRPs only support ISE rather than
> Vivado.

Thank you very much for the links. That certainly clarifies things.
Looking the the HDL collection I'm a little unsure of how I should
proceed. There is a lot of stuff in there that likely doesn't apply to
me but I'm not sure what to axe and how to interface with it. Ultimately
this is all we are trying to accomplish:
      * My VHDL code generates a sequence of signed integers clocked at
        about 200MHz that needs to find it's way to the DAC.
      * We need access to the system clock.
      * We need to generate our own clock with a PLL on the FPGA and use
        that clock to control the DAC.
      * We need to somehow tell the daughterboard what frequency to mix
        our baseband up to.
      * We need to get the daughterboard receiver to downmix that signal
        and sample it with the ADC at a clock that we also control.
      * We don't need access to any other peripherals. All data being
        transmitted will be generated randomly on the FPGA and received
        on the FPGA.
To me this must be super simple (relatively) since we only need to talk
to the DAC/ADC, daughterboard and access clocking mechanisms. The goal
of this is simply to generate a test signal we can look at on a spectrum
analyzer. Surely this would only involve a few HDL files and some pin
constraints? Any suggestions beyond what you've said thus far on
proceeding? Is there any sort of block diagram showing which verilog
modules are responsible for interfacing with which peripherals?
	Eddie Carle

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