[USRP-users] B210 RF DC Offset Calibration Failure

Perelman, Nathan nperelman at LGSInnovations.com
Mon Dec 1 18:58:43 EST 2014

As advertised by the driver, the error does go away when I request a master
clock rate of 56 MHz. Other values between 56 and 61.44 MHz did not work (I
tried 57, 58, and 60). I was hoping to be able to sample at 61.44 MHz for my



From: Ian Buckley [mailto:ianb at ionconcepts.com] 
Sent: Monday, December 1, 2014 6:16 PM
To: Perelman, Nathan
Cc: usrp-users at lists.ettus.com
Subject: Re: [USRP-users] B210 RF DC Offset Calibration Failure


This is a vague answer since I've never worked on this aspect of AD9361 and
someone may respond with a better response...


My recollection is that despite the actually radio being spec'ed to
61.44MHz, experience demonstrated that some of the internal algorithms that
perform calibrations start to have problems converging above 56MHz, which
generally results in larger elapsed times before the device is ready to by
used after configuration. Thus the origins of the warning message UHD gives
for rates >56MHz. I don't recall hearing a good reason "why" this should be
so from any ADI engineering folks.


So perhaps slow to converge manifests as failed to converge for some
possible configurations? What happens if you back it off a little from the
limit..say 61.0HMz?





On Dec 1, 2014, at 1:58 PM, "Perelman, Nathan via USRP-users"
<usrp-users at lists.ettus.com> wrote:

I'm seeing this error attempting to use a B210 with a master clock rate of
61.44 MHz. This is with UHD 3.8.0. I've been just trying to test it out with
the benchmark_rate application, but this is what happens:


$ ./benchmark_rate --rx_rate 61.44e6 --channels 0 --args
"master_clock_rate=61.44e6" --rx_cpu=sc16

linux; GNU C++ version 4.8.3 20140624 (Red Hat 4.8.3-1); Boost_105500;



Creating the usrp device with: master_clock_rate=61.44e6...

-- Operating over USB 3.

-- Detecting internal GPSDO.... Found an internal GPSDO

-- Initialize CODEC control...

-- Initialize Radio control...

-- Performing register loopback test... pass

-- Performing register loopback test... pass

-- Performing CODEC loopback test... pass

-- Performing CODEC loopback test... pass

-- Asking for clock rate 61.440000 MHz


UHD Warning:

    The requested clock rate 61.440000 MHz may cause slow configuration.

    The driver recommends a master clock rate less than 56.000000 MHz.

Error: RuntimeError: [ad9361_device_t] RF DC Offset Calibration Failure



I get the same error for other rates I've tried in excess of 56 MHz. Any
idea what causes this error and what I could do to resolve it? Thanks.


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