[USRP-users] For help to fgpa image of usrp n210

Ian Buckley ianb at ionconcepts.com
Mon Dec 1 13:51:08 EST 2014

This isn't really a USRP problem, it's a Xilinx ISE problem, and if you are having difficulties understanding Chipscope you should seek help on the Xilinx forums.
Generally if chipscope appears not to work at all make sure:
1) It's connected to a clock that is actually running. if Analyzer can find an ICON and the ILA blocks you added but you can not use the trigger immediately function then this is most likely your problem.
2) That the logic you created ah been added and hasn't been optimized away by ISE because of a small coding error - Check the log files.
3) That your modified RTL design still passes timing.


On Nov 29, 2014, at 4:40 AM, hzc191025--- via USRP-users <usrp-users at lists.ettus.com> wrote:

> I want to check some signal in fpga, so generate the bit stream file, and burn it by JTAG, Moinitor some signal in the chipscope
> Then, burning is finished, receiver program in computer is running well, but chipscope signal can be triggered
> I do not why?
> Thank you for your help!!
> hzc191025 at gmail.com
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> USRP-users mailing list
> USRP-users at lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

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