[USRP-users] Direct Programming the FPGA
ianb at ionconcepts.com
Mon Dec 1 13:45:27 EST 2014
You are right to be concerned about the amount of work involved in building an X300 image from scratch.
Some of the interfaced logic use's high speed interfaces and/or has tricky programming and there's been a vast amount of man hours spent on getting that all working well.
All the HDL code is published here: https://github.com/EttusResearch/fpga/tree/master look under the usrp3 directory for X300 related code.
Most X300 peripheral programming is actually done on the host from the UHD code base, just the actual SPI/I2C controllers etc are on the X300.
In most cases such as your own it's possible to do a little creative hacking and insert your custom HDL into the Ettus HDL and then piggyback on all the work already done in UHD.
There is also a new Ettus methodology to customize the X300 HDL called RFNoC which might work for you: https://github.com/EttusResearch/uhd/wiki/RFNoC:-Getting-Started
I have built entirely custom FPGA designs for older USRP's such as the N210 which are simpler system designs and that might be another approach to consider if you don't need the full X300 performance/capacity. However older USRPs only support ISE rather than Vivado.
On Nov 28, 2014, at 7:58 PM, Eddie Carle via USRP-users <usrp-users at lists.ettus.com> wrote:
> I'm involved in some QPSK channel coding research and we're at a stage
> where we need to do a practical implementation test. Over the last few
> months I've been developing at set of VHDL modules to generated an
> encoded intermediate frequency QPSK signal and a Python interface to
> manage parameterization, synthesis, unit tests, and simulations. The
> interface front ends the Vivado Design Suite.
> We've been trying to decide on a piece of hardware to implement this and
> the USRP X300/310 seems to be the best option we've got out there. Most
> of the literature I've been reading seems to focus on using GNU Radio or
> some other front end to talk to the unit but our requirement will be to
> programme directly with a bit file generated from Vivado. I've been
> looking over the schematics of the unit and I'm realizing that writing
> the VHDL/Verilog code to interface with the peripherals attached to the
> FPGA would be a pretty huge job. Question is: is the HDL code for
> interfacing with these peripherals published? Either way, does anybody
> have any suggestions on how one might proceed to building a custom bit
> file in Vivado for this unit?
> Eddie Carle
> USRP-users mailing list
> USRP-users at lists.ettus.com
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