[USRP-users] Fwd: Testing the USRP2 FPGA code

sean rivera sean.rivera at colorado.edu
Fri Sep 20 11:21:06 EDT 2013


Yes the pre-existing data replaces live off the air signals. It is a simple
 capture from the default DSP-chain, that I know the results of.
Unfortunately my model needs around 1000 samples of 32 byte data to per
result it returns. In order to run a full simulation its around 30,000
times that which makes a test bench unfeasible. Previously I've tested it
by transmitting the data out through on USRP and then receiving it on
another, however that is not an optimal solution.


On Thu, Sep 19, 2013 at 6:32 PM, Ian Buckley <ianb at ionconcepts.com> wrote:

> The "pre-existing data" replaces live off the air signals?
>
> In which case why not just simulate your module in Verilog with a test
> bench?
>
> There are a variety of ways to do something similar in the live FPGA image
> but it's hard to make a detailed suggestion without knowing more about the
> data you wish to feed the block, or how the block will interact with other
> logic.
>
> On Sep 19, 2013, at 4:57 PM, sean rivera <sean.rivera at colorado.edu> wrote:
>
> > Hello list,
> >
> > I'm having a bit of a challenge in testing custom firmware for the FPGA.
> For my custom module I have a Matlab module used to determine position
> coordinates over GPS that I have converted to Verilog. In order to test
> this module I would like to take preexisting data, and pass it into my
> Verilog code, either using the SD card or Ethernet of the N210. Is there
> anyway to do this?
> >
> > Thanks for you help,
> > --
> > ~Sean Rivera
> > ECEN, CSCI,APPM
> > _______________________________________________
> > USRP-users mailing list
> > USRP-users at lists.ettus.com
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>


-- 
~Sean Rivera
ECEN, CSCI,APPM
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