[USRP-users] USRP E100 FPGA - OMAP communication

Muez Berhane Reda m.reda at isispace.nl
Mon Sep 9 10:54:16 EDT 2013


On 9/9/2013 4:35 PM, Philip Balister wrote:
> On 09/09/2013 09:50 AM, Muez Berhane Reda wrote:
>> On 9/9/2013 3:31 PM, Philip Balister wrote:
>>> On 09/09/2013 08:44 AM, Muez Berhane Reda wrote:
>>>> Thank you for the reply Philip,
>>>>
>>>> 1- The FPGA is memory mapped to GPMC chip select 4, where it writes the
>>>> samples to and DMA of ARM is responsible for copying from GPMC to the
>>>> ring buffers available.
>>>>        So, are we assuming the DMA copy is faster than the rate FPGA is
>>>> writing to the GPMC memory?
>>> The DMA is reading samples from the FPGA and writing them to RAM. The
>>> FPGA cannot bus master, so all the transfers are done via the OMAP DMA
>>> controller.
>> Do you mean the FPGA have its own memory or is it memory mapped to GPMC CS?
> There is some FPGA memory that stores samples until the ARM copied from
> them into the OMAP memory (which is available to the ARM and DSP)

1- Ok, So if I use DSP, instead of ARM, I have to copy from that FPGA memory, not from GPMC CS 4?

2- How is the ARM informing FPGA it have finished DMA copying from the FPGA memory? because I have to do the same after EDMA copy from DSP.

>
>>>> 2- I am working on offloading this task to c64x DSP on the OMAP3530, but
>>>> I keep reading the same block of samples (using EDMA) on every GPIO
>>>> interrupt received by the DSP. This is when GPIO interrupt enable (IE)
>>>> registers of ARM and DSP are both set. When I disable the IE for ARM, I
>>>> only get 1 data ready  GPIO interrupt to DSP at the beginning of the
>>>> program.
>>>>
>>> I'm not following you. There is a GPIO from the FPGA that tells the ARM
>>> when there is data available to read.
>> Yes, that GPIO pin tells the ARM when there is data available to read.
>> In addition to that,
>> The GPIO module can also send event(interrupt) to IVA2.2 Interrupt
>> Controller(DSP) of the OMAP. It have two IE registers for both ARM and DSP.
>> The default is, IE for DSP is disabled. I enabled it and I started
>> getting GPIO interrupts to DSP and I
>> used EDMA to copy the samples from the GPMC CS4 memory address.
>>
>> But the problem is at this time both ARM (via DMA) and DSP (via EDMA)
>> are accessing the same
>> memory locations, which I think is causing the problem of reading the
>> same block of samples from the GPMC memory.
>>
>> As a result I disabled the ARM's IE register of the Data_Ready GPIO pin. I
>> only get 1 data ready  GPIO interrupt to DSP at the beginning of the
>> program. I don't know why.
>>
>> I hope I make myself clear.
>>
> It sounds like you need to unload the ARM driver with rmmod so it does
> not conflict with your DSP based driver.

Yes, I am doing that after loading the FPGA image and issuing stream command from the UHD program.

> Philip
>
>
>>> Philip
>>>
>>>> regards,
>>>> Muez
>>>>
>>>> On 9/9/2013 2:29 PM, Philip Balister wrote:
>>>>> On 09/09/2013 06:27 AM, Muez Berhane Reda wrote:
>>>>>> Dear all,
>>>>>>
>>>>>> I have a question on USRP E100.
>>>>>>
>>>>>> The FPGA sends GPIO interrupts to Gumstix (OMAP) to notify that
>>>>>> Data is
>>>>>> available for it to read.
>>>>>> How does the FPGA know that the OMAP system have finished
>>>>>> accessing(reading from) the GPMC CS , so that it can write to that
>>>>>> memory location again. What is the signaling mechanism used to prevent
>>>>>> FPGA from writing new samples while the DMA of OMAP is on the
>>>>>> process of
>>>>>> copying the old samples?
>>>>> There is a large buffer in the OMAP RAM that samples are copied form
>>>>> the
>>>>> FPGA to memory, so there are multiple destination buffers available for
>>>>> the fpga to write to. As these buffers are processed by the ARM, they
>>>>> are returned to the pool of buffers available for the FPGA to write
>>>>> samples to.
>>>>>
>>>>> Philip
>>>>>
>>>>>> regards,
>>>>>>
>> regards,
>> Muez
>>
thank you,

regards,
Muez

-- 
Muez Berhane Reda,

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