[USRP-users] USRP E100 FPGA - OMAP communication
philip at opensdr.com
Mon Sep 9 09:31:12 EDT 2013
On 09/09/2013 08:44 AM, Muez Berhane Reda wrote:
> Thank you for the reply Philip,
> 1- The FPGA is memory mapped to GPMC chip select 4, where it writes the
> samples to and DMA of ARM is responsible for copying from GPMC to the
> ring buffers available.
> So, are we assuming the DMA copy is faster than the rate FPGA is
> writing to the GPMC memory?
The DMA is reading samples from the FPGA and writing them to RAM. The
FPGA cannot bus master, so all the transfers are done via the OMAP DMA
> 2- I am working on offloading this task to c64x DSP on the OMAP3530, but
> I keep reading the same block of samples (using EDMA) on every GPIO
> interrupt received by the DSP. This is when GPIO interrupt enable (IE)
> registers of ARM and DSP are both set. When I disable the IE for ARM, I
> only get 1 data ready GPIO interrupt to DSP at the beginning of the
I'm not following you. There is a GPIO from the FPGA that tells the ARM
when there is data available to read.
> On 9/9/2013 2:29 PM, Philip Balister wrote:
>> On 09/09/2013 06:27 AM, Muez Berhane Reda wrote:
>>> Dear all,
>>> I have a question on USRP E100.
>>> The FPGA sends GPIO interrupts to Gumstix (OMAP) to notify that Data is
>>> available for it to read.
>>> How does the FPGA know that the OMAP system have finished
>>> accessing(reading from) the GPMC CS , so that it can write to that
>>> memory location again. What is the signaling mechanism used to prevent
>>> FPGA from writing new samples while the DMA of OMAP is on the process of
>>> copying the old samples?
>> There is a large buffer in the OMAP RAM that samples are copied form the
>> FPGA to memory, so there are multiple destination buffers available for
>> the fpga to write to. As these buffers are processed by the ARM, they
>> are returned to the pool of buffers available for the FPGA to write
>> samples to.
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