[USRP-users] Changing FPGA Code in USRP N210
jinujayachandran at gmail.com
Sat Feb 23 13:18:01 EST 2013
Thanks for the replies.
I had changed the Makefile.N210R4 as Florian had suggested to include my
custom block after the ddc chain in the receiver module. I want to confirm
whether it is the right place to put my FFT block. So what I did was, I
wrote a simple module in the custom_dsp_rx.v file which takes in
ddc_out_sample and shifts the sample to left by 16 bits (ddc_out_sample <<
16) and assign it to bbc_sample. So basically I am removing the In Phase
components from the sample and corrupting the data (am I right?). I had
also latched the bb_strobe and ddc_out_enable signals.
Then I used the /digital/narrowband example from the gnuradio to transmit a
text file from a remote machine and receive it on host machine. If my
module had worked, the text file should NOT have received correctly. But
surprisingly the data sent from the transmitter is received exactly same at
the receiver host. (I had also tried with changing the values of
ddc_out_sample in many ways and assigning it to bbc_sample. It may be a
stupid way of testing, but I would like to try out things).
1) Is the above way of testing correct ?.
2) If not, how can I test the scenario of changing the received data in
FPGA before putting in my FFT code?
3) Do I need to do anything with set_stb, set_addr and set_data signals?
4) Is the narrowband example enough to display it in the host machine ?
5) Is there anything else I am missing?
Thanks and Regards
On 15 February 2013 21:14, Ben Reynwar <ben at reynwar.net> wrote:
> I've had a crack at getting an FFT working on the B100 FPGA. It's not
> working yet, but it might still be useful to check out.
> The code is at:
> I do as much debugging on possible using the Icarus simulator and use
> MyHDL to interface with it so I can write my QA code in python.
> On Fri, Feb 15, 2013 at 2:31 AM, Jinu Jayachandran
> <jinujayachandran at gmail.com> wrote:
> > Hi,
> > I am trying to implement an FFT algorithm in USRP N210 R4 FPGA. I would
> > like to know if the procedure I am following to build the FPGA image is
> > correct. The procedure is as follows
> > 1) Downloaded the images from
> > http://code.ettus.com/redmine/ettus/projects/uhd/repository
> > 2) I have edited the make file in the images folder to make images only
> > N series firmware and N210 FPGA
> > 3) Then I did a 'make images' in the image folder
> > 4) It generated a .bin files for firmware and FPGA in /images/images
> > I am facing the following problems
> > 1) The building of the fpga image took around 30 minutes in my machine.
> > whenever I edit the FPGA code I should wait for 30 minutes before I want
> > test if it is working properly. Is this the normal time it takes to
> build ?.
> > Can I reduce the time to build image in some way?
> > 2) I would like to know where to put by FFT verilog code for the
> receiver in
> > the FPGA?. From the code review I have done, my understanding is to put
> > code in /usrp2/top/N2x0/u2plus_core.v. And I need to get the sample_rx0
> > value and strobe_rx0 values from the ddc_chain block as input to my FFT
> > block and give the output to vita_rx_chain. Is my understanding correct
> > (I tried to implement a simple code by taking the sample_rx0 from
> > ddc_chain, modify it and sent to vita_rx_chain. Then i used the
> > example in the gnuradio to check if there is any change in data. But
> > is no change and sometimes the receiver doesn't receive at all).
> > Please help
> > Thanks and Regards
> > Jinu
> > _______________________________________________
> > USRP-users mailing list
> > USRP-users at lists.ettus.com
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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