[USRP-users] Changing FPGA Code in USRP N210

Florian Schlembach florian.schlembach at tu-ilmenau.de
Wed Feb 20 09:04:33 EST 2013


>     2) I would like to know where to put by FFT verilog code for the
>     receiver in the FPGA?. From the code review I have done, my
>     understanding is to put the code in /usrp2/top/N2x0/u2plus_core.v.
>     And I need to get the sample_rx0 value and strobe_rx0 values from
>     the ddc_chain block as input to my FFT block and give the output to
>     vita_rx_chain. Is my understanding correct ?. (I tried to implement
>     a simple code by taking the sample_rx0  from ddc_chain, modify it
>     and sent to vita_rx_chain. Then i used the narrowband example in the
>     gnuradio to check if there is any change in data. But there is no
>     change and sometimes the receiver doesn't receive at all).
>
>
> This is a good place to do it.  Alternatively, you can modify
> ddc_chain.v to add your logic to the end of the RX processing.  Either
> way, however, it is important to understand the function of the 'run'
> input from the rx_control module.  This is directly controlled by the
> UHD logic to gate when to stream samples over sample_rx0/strobe_rx0, and
> acts as a sort of enable for much of the ddc_chain logic.  If you modify
> the logic you will have to ensure that anything inserted between
> ddc_chain and rx_control manages this properly, and also accounts for
> any pipeline delay within your new logic.
>
> Johnathan

Neither of both options is the most straightforwarded options anymore 
since was designed a placeholder for some custom logic. It got quite 
"easy" if you know how to do it. :-)
Have a look at this README file:

https://github.com/EttusResearch/UHD-Mirror/blob/master/fpga/README.txt

For your purpose, you should proceed as followed:

1. Modify Makefile.N210:

# set me in a custom makefile
CUSTOM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../custom/, \
custom_dsp_rx.v \
))
CUSTOM_DEFS = RX_DSP0_MODULE=custom_dsp_rx

2. Implement your code into /custom/custom_dsp_rx.v
Depending on where you wanna perform fft (before or after the existing 
ddc chain, so full bandwidth or decimated) you have to grab the 
respective signals. Lets assume now your module should take effect after 
ddc, grab your     //strobed samples {I16,Q16} from the RX DDC chain 
signal ddc_out_sample that comes in with a ddc_out_strobe:

     input [31:0] ddc_out_sample,
     input ddc_out_strobe, //high on valid sample
     output ddc_out_enable, //enables DDC module

and send it further as the bb_sample with a bb_strobe being asserted:

     //strobbed baseband samples {I16,Q16} from this module
     output [31:0] bb_sample,
     output bb_strobe //high on valid sample

3. Validate your custom_dsp_rx.v with a testbench feeding your module 
with some stimulus signals

4. Go synthesise it!

5. Burn it onto your device and hope everything works! :)






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