[USRP-users] Changing FPGA Code in USRP N210

Jinu Jayachandran jinujayachandran at gmail.com
Fri Feb 15 04:31:50 EST 2013


Hi,

  I am trying to implement an FFT algorithm in USRP N210 R4 FPGA. I would
like to know if the procedure I am following to build the FPGA image is
correct. The procedure is as follows

1) Downloaded the images from
http://code.ettus.com/redmine/ettus/projects/uhd/repository
2) I have edited the make file in the images folder to make images only for
N series firmware and N210 FPGA
3) Then  I did a 'make images' in the image folder
4) It generated a .bin files for firmware and FPGA in /images/images folder

I am facing the following problems

1) The building of the fpga image took around 30 minutes in my machine. So
whenever I edit the FPGA code I should wait for 30 minutes before I want to
test if it is working properly. Is this the normal time it takes to build
?. Can I reduce the time to build image in some way?

2) I would like to know where to put by FFT verilog code for the receiver
in the FPGA?. From the code review I have done, my understanding is to put
the code in /usrp2/top/N2x0/u2plus_core.v. And I need to get the sample_rx0
value and strobe_rx0 values from the ddc_chain block as input to my FFT
block and give the output to vita_rx_chain. Is my understanding correct ?.
(I tried to implement a simple code by taking the sample_rx0  from
ddc_chain, modify it and sent to vita_rx_chain. Then i used the narrowband
example in the gnuradio to check if there is any change in data. But there
is no change and sometimes the receiver doesn't receive at all).

Please help

Thanks and Regards
Jinu
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