[USRP-users] Addressing custom logic in fpga

Diego Montemayor diegomontemayors at gmail.com
Wed Feb 13 16:41:38 EST 2013


Thanks, this is what I was looking for.

On Wed, Feb 13, 2013 at 8:57 AM, Johnathan Corgan
<johnathan at corganlabs.com>wrote:

> On Tue, Feb 12, 2013 at 10:40 PM, Ian Buckley <ianb at ionconcepts.com>wrote:
>
>
>> If you do ever add further logic to the Verilog and find you are running
>> short off address space, then it is quite simple to add a new settings_bus
>> bridge, identical to the existing one to one of the unused Wishbone bus
>> slave locations so that you have an entire new settings bus to use.
>>
>
> There is already a dedicated settings bus in place specifically for use in
> custom designs, which allows the user to create up to 256 32-bit write-only
> configuration registers that exist outside the address space of the
> standard settings bus.
>
> In the top level module (e.g., u2plus_core.v), there are wires
> 'set_addr_user', 'set_data_user', and 'set_stb_user', with the same
> semantics as the standard configuration bus.  To use these in a custom
> design, one creates new instances of 'settings_reg' but connects their
> inputs to this set of wires instead.
>
> To initiate a write cycle, from the host UHD interface one issues a call
> to:
>
>  void set_user_register(const boost::uint8_t addr, const boost::uint32_t
> data, size_t mboard = ALL_MBOARDS)
>
> ...from an instance of uhd::usrp::multi_usrp.  This call is also part of
> the GNU Radio UHD source and sink blocks.
>
> Johnathan
>
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>
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