[USRP-users] Addressing custom logic in fpga

Diego Montemayor diegomontemayors at gmail.com
Wed Feb 13 01:56:53 EST 2013


This would be for the N210.  I know there are two DDCs available but our
design could still benefit from additional ones.  What changes would I need
to make in the host side to access the new DDCs?  Could it be as simple as
initializing the USRP with an additional DDC and adding the new addresses
in the relevant files?

ie.

// create rx dsp control objects

_mbc[mb].rx_dsps.push_back(rx_dsp_core_200::make(_mbc[mb].wbiface,
U2_REG_SR_ADDR(SR_RX_DSP0), U2_REG_SR_ADDR(SR_RX_CTRL0), USRP2_RX_SID_BASE
+ 0, true));

_mbc[mb].rx_dsps.push_back(rx_dsp_core_200::make(_mbc[mb].wbiface,
U2_REG_SR_ADDR(SR_RX_DSP1), U2_REG_SR_ADDR(SR_RX_CTRL1), USRP2_RX_SID_BASE
+ 1, true));

// New DDC added here
// SR_RX_DSP2 and SR_RX_CTRL2 are declared accordingly

_mbc[mb].rx_dsps.push_back(rx_dsp_core_200::make(_mbc[mb].wbiface,
U2_REG_SR_ADDR(SR_RX_DSP2), U2_REG_SR_ADDR(SR_RX_CTRL2), USRP2_RX_SID_BASE
+ 2, true));


On Wed, Feb 13, 2013 at 1:40 AM, Ian Buckley <ianb at ionconcepts.com> wrote:

>
> On Feb 12, 2013, at 6:16 PM, Marcus D. Leech <mleech at ripnet.com> wrote:
>
>  Hello,
>
>  I'm working on a project that involves modifying the fpga contents and
> adding an additional DDC that works in parallel to the first DSP block.
>  The idea would be to sample the same data at two different center
> frequencies.  I'd like to be able to program these frequencies separately
> through the API but am worried there may not be enough room in the address
> map.  Is there  a simple way to do this without making many changes to the
> API?  Would it be possible to configure them under the same address?
>
>  Thanks,
>
>  Diego
>
>
> _______________________________________________
> USRP-users mailing listUSRP-users at lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>  Which base platform?
>
> There's already dual-DDC support in some of the platforms, the N2XX in
> particular.
>
>
>
> --
> Principal Investigator
> Shirleys Bay Radio Astronomy Consortiumhttp://www.sbrac.org
>
> Diego,
> As Marcus already pointed out, most of the current USRP's already have
> code that supports 2 independent receive DSP's including DDC's.
> If you do ever add further logic to the Verilog and find you are running
> short off address space, then it is quite simple to add a new settings_bus
> bridge, identical to the existing one to one of the unused Wishbone bus
> slave locations so that you have an entire new settings bus to use.
> -Ian
>
>
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>
>
>
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