[USRP-users] Addressing custom logic in fpga

Ian Buckley ianb at ionconcepts.com
Wed Feb 13 01:40:00 EST 2013


On Feb 12, 2013, at 6:16 PM, Marcus D. Leech <mleech at ripnet.com> wrote:

>> Hello,
>> 
>> I'm working on a project that involves modifying the fpga contents and adding an additional DDC that works in parallel to the first DSP block.  The idea would be to sample the same data at two different center frequencies.  I'd like to be able to program these frequencies separately through the API but am worried there may not be enough room in the address map.  Is there  a simple way to do this without making many changes to the API?  Would it be possible to configure them under the same address?
>> 
>> Thanks,
>> 
>> Diego
>> 
>> _______________________________________________
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> Which base platform?
> 
> There's already dual-DDC support in some of the platforms, the N2XX in particular.
> 
> 
> 
> -- 
> Principal Investigator
> Shirleys Bay Radio Astronomy Consortium
> http://www.sbrac.org
Diego, 
As Marcus already pointed out, most of the current USRP's already have code that supports 2 independent receive DSP's including DDC's.
If you do ever add further logic to the Verilog and find you are running short off address space, then it is quite simple to add a new settings_bus bridge, identical to the existing one to one of the unused Wishbone bus slave locations so that you have an entire new settings bus to use.
-Ian


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