[USRP-users] Addressing custom logic in fpga
diegomontemayors at gmail.com
Tue Feb 12 21:03:41 EST 2013
I'm working on a project that involves modifying the fpga contents and
adding an additional DDC that works in parallel to the first DSP block.
The idea would be to sample the same data at two different center
frequencies. I'd like to be able to program these frequencies separately
through the API but am worried there may not be enough room in the address
map. Is there a simple way to do this without making many changes to the
API? Would it be possible to configure them under the same address?
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