[USRP-users] Using multiple RX DDC chains on USRP2

Roy Thompson rthompso at gmail.com
Thu Feb 7 16:30:02 EST 2013


Thanks, will that work if the chains have different sample rates?
There is a comment in multi_usrp.hpp stating that all channels must
have the same rate, but it's not clear what causes the limitation
since it looks like it is possible to set the rate for individual
channels with set_rx_rate().

-Roy

On Thu, Feb 7, 2013 at 4:17 PM, Josh Blum <josh at ettus.com> wrote:
>
>
> On 02/07/2013 02:49 PM, Roy Thompson wrote:
>> I am starting to look through some of the FPGA code for the USRP2 and
>> I noticed that there are 2 RX DDC chains.  I would like to be able to
>> use one of the chains to do standard DDC processing, and I would like
>> to modify the second chain to do custom processing on the same A/D
>> channel.  The output sample rate for the second chain will be
>> different from the first. Is it possible to configure the UHD driver
>> to support this configuration and allow for receiving from both
>> chains?
>>
>
> The rx_multi_samples example can show you how to use two DDC chains. If
> you had a WBX for example with frontend (named 0), this would map
> frontend 0 located on the first and only daughterboard (named A) to DSP0
> and DSP1 --subdev="A:0 A:0"
>
> see the --help for more.
>
>> std::cout <<
>>         "    This is a demonstration of how to receive aligned data from multiple channels.\n"
>>         "    This example can receive from multiple DSPs, multiple motherboards, or both.\n"
>>         "    The MIMO cable or PPS can be used to synchronize the configuration. See --sync\n"
>>         "\n"
>>         "    Specify --subdev to select multiple channels per motherboard.\n"
>>         "      Ex: --subdev=\"0:A 0:B\" to get 2 channels on a Basic RX.\n"
>>         "\n"
>>         "    Specify --args to select multiple motherboards in a configuration.\n"
>>         "      Ex: --args=\"addr0=192.168.10.2, addr1=192.168.10.3\"\n"
>>         << std::endl;
>
>
> See this readme, there is a place where it should be convenient to
> replace the DDC with custom logic:
>
> http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/README.txt
>
> -josh
>
>> Thanks,
>> Roy
>>
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>>
>
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