[USRP-users] gain setting and clipping

Josh Blum josh at ettus.com
Thu Feb 7 15:12:07 EST 2013



On 02/06/2013 02:09 AM, Sivan Toledo wrote:
> Hi,
> 
> I am trying to find good settings of the gain and LO frequency in order to
> detect weak signals in the presence of strong out-of-band (but nearby)
> signals with an N200+WBX.
> 
> My obvious goal is to use the highest gain setting that does not result in
> saturation in the ADCs and in the arithmetic in the FPGA.
> 
> Does saturation/clipping always results in maximum values (near 32767 in
> absolute value) in the samples I get? Is this a reliable signal to reduce
> gain (or move the LO away so that interfering signals are attenuated by the
> anti-aliasing filters in the WBX)?
> 

32767 is the full scale of the ADC/DAC signals in the FPGA. The complex
magnitude of the signal should be less than 32767 to avoid clipping the
the FPGA DSP chain.

I should also point out that the clipping occurs in the CORDIC. So if
the DSP frequency (CORDIC frequency) is set to zero, then you can get
full scale though both I and Q.

With that in mind, you should be able to calibrate the saturation point
for your setup.

-josh

> Thanks, Sivan
> 
> 
> 
> _______________________________________________
> USRP-users mailing list
> USRP-users at lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> 




More information about the USRP-users mailing list