[USRP-users] Receive FPGA pipeline overflow?

Matt Ettus matt at ettus.com
Tue Apr 30 13:45:58 EDT 2013


The long story.

Others have answered well, but I will add some detail.  If a signal is
overrange, the ADCs will have correct clipping behavior, meaning anything
higher than max positive amplitude will register as maximum positive, and
the same for negative.  You don't want to put in too strong of a signal
because you could blow something, of course.

All of the subsequent digital processing stages fall into one of 2 types of
behavior:

- No matter what the input signal, the output cannot overflow (i.e. they
are inherently safe).  The CORDIC and CIC fall in to this category, for
example.

- Some strong signals could cause overflow, but it is very unlikely, AND we
handle those cases by clipping properly.  DC offset and IQ balance
correction fall in this category.

It would only be a problem if we allowed strong signals to overflow without
clipping, which could have all sorts of bad results, like negative output
when the signal is really a strong positive, random noise, etc.  This will
not occur in the standard DSP blocks we ship.

Matt


On Tue, Apr 30, 2013 at 12:38 AM, Per Zetterberg <perz at kth.se> wrote:

>
> Hi List,
>
>
> If I have a strong signal, connected to say LFRX (i.e a base-band signal).
> Is it then possible (on the USRP N210) that the FPGA pipeline may overflow.
> I mean the analog signal is still within the range of the ADC but the
> digital stages overflow somewhere. Is there anything I can do about it? for
> instance post-correction?
>
> BR/
> Per
> _______________________________________________
> USRP-users mailing list
> USRP-users at lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/attachments/20130430/368c6226/attachment-0002.html>


More information about the USRP-users mailing list