[USRP-users] Receive FPGA pipeline overflow?

Marcus D. Leech mleech at ripnet.com
Tue Apr 30 13:12:15 EDT 2013


On 04/30/2013 03:38 AM, Per Zetterberg wrote:
> Hi List,
>
>
> If I have a strong signal, connected to say LFRX (i.e a base-band signal). Is it then possible (on the USRP N210) that the FPGA pipeline may overflow. I mean the analog signal is still within the range of the ADC but the digital stages overflow somewhere. Is there anything I can do about it? for instance post-correction?
>
> BR/
> Per
>
I don't believe that integer overflow is a possibility in the FPGA 
signal chain, even with "bit growth" due to the CIC decimators, that's 
all accounted
   for.

If you're sampling strong signals, you can get into non-linear operating 
regions in the analog bits -- there's a differential amplifier on the
   LF_RX for example.

Also, if you aren't band-limiting your input to handily-below the 
Nyquist frequency (50Mhz, in the case of the N210, because the ADC 
samples at
   100Msps), then you'll get aliases folded into the signals after 
they're sampled.

If your signals are so strong that you're worried about overflow, use an 
attenuator in front of the daughtercard.


-- 
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org






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