[USRP-users] Receive FPGA pipeline overflow?
mike at scanoo.com
Tue Apr 30 12:58:02 EDT 2013
My understanding is that if your signal is within the range of the ADC then
it will processed by the Ettus N210's FPGA without issue. If you are
having an issue with sampling the strong signal in question then could this
be due to harmonics lying outside the passband. Using an Ettus USRP N210
with a LFRX daughterboard (0 - 30MHz frequency range) you can sample with
an RF bandwidth of 25MHz (14 bit samples) or 30MHz (8 bit samples). With
the LFRX, strong signals above the passband will alias and fold over
themselves if you don't have a lowpass filter in place.
Mike Jameson M0MIK BSc MIET
Email: mike at scanoo.com
On 30 April 2013 08:38, Per Zetterberg <perz at kth.se> wrote:
> Hi List,
> If I have a strong signal, connected to say LFRX (i.e a base-band signal).
> Is it then possible (on the USRP N210) that the FPGA pipeline may overflow.
> I mean the analog signal is still within the range of the ADC but the
> digital stages overflow somewhere. Is there anything I can do about it? for
> instance post-correction?
> USRP-users mailing list
> USRP-users at lists.ettus.com
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