[USRP-users] Receive FPGA pipeline overflow?

Per Zetterberg perz at kth.se
Tue Apr 30 03:38:36 EDT 2013

Hi List,

If I have a strong signal, connected to say LFRX (i.e a base-band signal). Is it then possible (on the USRP N210) that the FPGA pipeline may overflow. I mean the analog signal is still within the range of the ADC but the digital stages overflow somewhere. Is there anything I can do about it? for instance post-correction?


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