[USRP-users] Custom Block in FPGA code of USRP N210

Florian Schlembach florian.schlembach at tu-ilmenau.de
Wed Apr 3 04:19:43 EDT 2013


How did you actually try to implement your custom logic? Here are some 
instructions how you can do it (I recycled them from some old posts here 
on the mailing list):

Have a look at the following README file:

https://github.com/EttusResearch/UHD-Mirror/blob/master/fpga/README.txt

For your purpose, you should proceed as followed:

1. Modify Makefile.N210:

# set me in a custom makefile
CUSTOM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../custom/, \
custom_dsp_rx.v \
))
CUSTOM_DEFS = RX_DSP0_MODULE=custom_dsp_rx

2. Implement your code into /custom/custom_dsp_rx.v
Depending on where you wanna perform fft (before or after the existing 
ddc chain, so full bandwidth or decimated) you have to grab the 
respective signals. Lets assume now your module should take effect after 
ddc, grab your     //strobed samples {I16,Q16} from the RX DDC chain 
signal ddc_out_sample that comes in with a ddc_out_strobe:

     input [31:0] ddc_out_sample,
     input ddc_out_strobe, //high on valid sample
     output ddc_out_enable, //enables DDC module

and send it further as the bb_sample with a bb_strobe being asserted:

     //strobbed baseband samples {I16,Q16} from this module
     output [31:0] bb_sample,
     output bb_strobe //high on valid sample

3. Validate your custom_dsp_rx.v with a testbench feeding your module 
with some stimulus signals

4. Go synthesise it!

5. Burn it onto your device and hope everything works!





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