[USRP-users] Purpose of 24-bit CORDIC in DDC chain?

Ian Buckley ianb at ionconcepts.com
Wed Apr 3 03:29:08 EDT 2013

Florian, Your understanding at this point is very good: The CIC provides arbitrary programable decimation at very little FPGA resource usage but has very significant pass band roll off. The two half bands have fixed decimation of 2 each but have very linear passband response. Having the Halfbands cascaded after the CIC allows us to keep the total system passband within the largely linear portion of the CIC frequency response…thus the reason it is highly desirable in practical applications using USRPs to have a total system decimation within the USRP that factors by 4 so that both Halfbands can be enabled…..further decimation (often with awkward ratio's) that suit the particular application can then be performed in GNURadio where the now reduced sample rate makes it computationally feasible. The reason by the way that the two halfbands are different implementations is that the small halfband can sustain a throughput of one input sample per clock cycle, where as the large halfband can only sustain a throughput of one input sample every two clock cycles because it reuses the physical multipliers with different coefficients to form more logical taps without doubling the size of the hardware.

In terms of the setting registers configuring the DSP's, yes the ZPU is responsible for actually writing them, but most of the intelligence behind calculating the programmed values is indeed implemented in UHD code on the Host.

On Apr 2, 2013, at 10:33 PM, Florian Schlembach <florian.schlembach at tu-ilmenau.de> wrote:

> Thanks, Ian, that already helps a lot.
> Marcus and me did already sent some messages to each other. Unfortunately, they didn't make it through to the list. I always get the error "Message has implicit destination" and the message waits for approval of the list administrator. By that, already some of my messages got lost.
> But back to topic: I try to comprehend and describe the functionality of the ddc chain (for my master thesis). here is what Marcus and me wrote so far:
> Me:
> "I see the register phase_inc coming being read from a settings_register
> and fed into the CORDIC. Is the fine tuning being controlled by the ZPU
> or UHD?"
> Marcus:
> "UHD does the necessary calculations on the host, and programs the registers accordingly.
> The CIC decimator always runs -- that's what provides decimation, and then the half-band filters are used, AFAIR, to do some cleanup after the CIC decimators.
> But any of the Ettus engineering team can correct me."
> Me:
> "One last thing regarding the chosen rate:  I am wondering which decimation filters are activated at a given decimation rate. Matt already commented on that point on the list.
> If the decimation rate is:
> - multiples of 4: both of the Halfband filters is active, CIC deactivated
> - multiplies of 2: only second (large) Halfband filter is activated, CIC deactivated"
> Now, I had a look into the UHD code (UHD/host/lib/usrp/usrp2/rx_dsp_core_200.cpp) and found out the following: If decim_rate is a:
> -multiple of 2: HB1 activated, HB2 and CIC deactivated
> -multiple of 4: Both HB1 and HB2 activated, CIC deactivated
> -any other odd number: decim_rate is decomposed into multiples of 2, the residual decimation is then performed by the CIC
> The CIC is a poor roll-off but is, in turn, freely programmable. HB have a better roll-off but the decimation rate is fixed to multiples of 2.
> Is my understanding right?
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