[USRP-users] Purpose of 24-bit CORDIC in DDC chain?

Florian Schlembach florian.schlembach at tu-ilmenau.de
Wed Apr 3 01:33:46 EDT 2013

Thanks, Ian, that already helps a lot.
Marcus and me did already sent some messages to each other. 
Unfortunately, they didn't make it through to the list. I always get the 
error "Message has implicit destination" and the message waits for 
approval of the list administrator. By that, already some of my messages 
got lost.

But back to topic: I try to comprehend and describe the functionality of 
the ddc chain (for my master thesis). here is what Marcus and me wrote 
so far:
"I see the register phase_inc coming being read from a settings_register
and fed into the CORDIC. Is the fine tuning being controlled by the ZPU
or UHD?"

"UHD does the necessary calculations on the host, and programs the 
registers accordingly.

The CIC decimator always runs -- that's what provides decimation, and 
then the half-band filters are used, AFAIR, to do some cleanup after the 
CIC decimators.

But any of the Ettus engineering team can correct me."

"One last thing regarding the chosen rate:  I am wondering which 
decimation filters are activated at a given decimation rate. Matt 
already commented on that point on the list.
If the decimation rate is:
- multiples of 4: both of the Halfband filters is active, CIC deactivated
- multiplies of 2: only second (large) Halfband filter is activated, CIC 

Now, I had a look into the UHD code 
(UHD/host/lib/usrp/usrp2/rx_dsp_core_200.cpp) and found out the 
following: If decim_rate is a:
-multiple of 2: HB1 activated, HB2 and CIC deactivated
-multiple of 4: Both HB1 and HB2 activated, CIC deactivated
-any other odd number: decim_rate is decomposed into multiples of 2, the 
residual decimation is then performed by the CIC

The CIC is a poor roll-off but is, in turn, freely programmable. HB have 
a better roll-off but the decimation rate is fixed to multiples of 2.

Is my understanding right?

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