[USRP-users] USRP buffering and latencies
josh at ettus.com
Sun Sep 30 19:11:25 EDT 2012
On 09/30/2012 03:26 AM, Usrp IITM wrote:
> I am trying to find out how USRP implements data buffers in the hardware.
> I have a few questions regarding this:
> 1) Do the USRP and the host (computer) communicate by UDP? Does the UHD
> use VITA49 as encapsulation above the UDP layer?
The packets for the network devices are simple VITA49 on top of UDP
datagrams. Some notes on this:
> 2) Once the packet (udp) reaches the USRP, where does the USRP store the
> a) Does it have a circular (or a normal) buffer?
> b) What is the size of this buffer? Can this size be changed?
> c) Does the USRP read from this buffer continuously (at the
> sampling rate)? Or does it wait for the buffer to get full?
---On transmit, there is a 1MB SRAM on the USRP which is used as a
sample FIFO. When this buffer fills, the API call to
usrp_tx_stream->send(...) will actually block until there is space
available on the USRP.
A software change could be used to shrink how much SRAM can be filled
with samples, but there is no way to increase the buffering without
swapping out the RAM with something larger.
The USRP will read from this SRAM ASAP when the TX DSP is consuming samples.
---On receive. There is a rather large kernel socket buffer. By default
the UHD sizes it to 50MB, but it can be arbitrary. When the buffer is
full, UDP datagrams are dropped.
> 3) What is the typical latency of a packet (UDP) to reach the USRP
> (assuming default settings with almost zero cpu load at the host)?
about 100us for gigabit ethernet. See the note about interrupt
More information about the USRP-users