[USRP-users] Unable to connect module

Tim Schuschies tim.schuschies at googlemail.com
Thu Sep 27 08:11:19 EDT 2012


OK guys thank you.
I got it. I didn't use my output signal in vita_tx_chain. After including
it in the behavior the compiler includes my module in the design.

2012/9/27 Tim Schuschies <tim.schuschies at googlemail.com>

> Thanks Ian and Josh,
> I wrote a simple wrapper, but it doesn't help. I also added another output
> signal and connected it with the vita_tx_chain (I added an input). So
> I definitively have a connected output and the input are connected too. My
> module stays unconnected. I will add the whole source code in the
> following. It would be great if someone could take a look at it. I don't
> see an error in the code, that could cause my problem. I don't understand
> the compiler... :/
>
> My module:
> entity carrier_sense is
>  Generic( THRESHOLD : integer := 32768);
>  Port ( sample_in : in  STD_LOGIC_VECTOR (31 downto 0);
>         clk : in  STD_LOGIC;
>         strobe : in STD_LOGIC;
>         rst : in  STD_LOGIC;
>         busy : out  STD_LOGIC;
> --Register
>  settings : in STD_LOGIC_VECTOR(31 downto 0);
> status_o : out STD_LOGIC_VECTOR(31 downto 0);
>  rssi_o : out STD_LOGIC_VECTOR(31 downto 0));
>
> end carrier_sense;
>
> architecture CarrierSense of carrier_sense is
>  signal rssi : std_logic_vector(15 downto 0);
> signal avg : std_logic_vector(15 downto 0);
>  signal status : std_logic_vector(15 downto 0);
> begin
>  busy <= '1';
> rssi <= complex_abs(sample_in(31 downto 16),sample_in(15 downto 0));
>  average : process(strobe,rst)
>  variable count,value : integer := 0;
> begin
>   if rst = '1' then
> count := 0;
>  value := 0;
>  elsif rising_edge(strobe) then
>  if count < 16 then
> count := count + 1;
>  value := value + to_integer(unsigned(rssi));
> else
>  value := value / 16;
> avg <= std_logic_vector(to_unsigned(value,16));
>  if to_integer(unsigned(avg)) < THRESHOLD then
> status(0) <= '1';
>  else
> status(0) <= '0';
>  end if;
> count := 0;
>  end if;
>  end if;
>  end process;
>  busy <= status(0);
> status_o(15 downto 0) <= status;
>  rssi_o(15 downto 0) <= rssi;
>
> end CarrierSense;
>
> The wrapper:
> entity carrier_wb_top is
>     Port ( sample_in : in  STD_LOGIC_VECTOR (31 downto 0);
>            clk : in  STD_LOGIC;
>            rst : in  STD_LOGIC;
>            strobe : in  STD_LOGIC;
>            busy : out  STD_LOGIC;
>            settings : in  STD_LOGIC_VECTOR (31 downto 0);
>            rssi_o : out  STD_LOGIC_VECTOR (31 downto 0);
>            status_o : out  STD_LOGIC_VECTOR (31 downto 0));
> end carrier_wb_top;
>
> architecture cs of carrier_wb_top is
>
> component carrier_sense is
>  port(
> sample_in : in std_logic_vector(31 downto 0);
>  clk : in std_logic;
> strobe : in std_logic;
>  rst : in std_logic;
> busy : out std_logic;
>  --register
> settings : in std_logic_vector(31 downto 0);
>  status_o : out std_logic_vector(31 downto 0);
> rssi_o : out std_logic_vector(31 downto 0));
> end component;
>
> begin
>
> carrier_sense0 : carrier_sense port map(
> sample_in => sample_in,
>  clk => clk,
> strobe => strobe,
>    rst => rst,
>    busy => busy,
> --Register
>  settings => settings,
> status_o => status_o,
>  rssi_o => rssi_o
> );
>
> end cs;
>
> And the port map of u2_core:
> wire[31:0] cs_settings,cs_rssi,cs_status;
> wire cs_busy;
> carrier_wb_top carrier_sense0
>  (
> .sample_in(sample_rx0),.clk(dsp_clk),.rst(dsp_rst),.strobe(strobe_rx0),.busy(cs_busy),
>    .settings(cs_settings),.rssi_o(cs_rssi),.status_o(cs_status));
>
> Thank you for your time.
> Tim
>
> 2012/9/26 Ian Buckley <ianb at ionconcepts.com>
>
>> Tim,
>> As an additional note…clearly the setting_reg's are not VHDL since they
>> are instantiations of existing Verilog code…they are pruned because they
>> have no connected outputs, having connected inputs will not stop pruning.
>> In the case of sr_cs_rssi_reg and sr_cs_settings_reg this will always
>> occur even after you solve the pruning of the carrier_sense module.
>> In addition, a different but related issue you haven't noticed
>> yet…setting reg's are Write-Only, you can not use them to read values as
>> part of the memory map…to do this you have two choices, the wb_readback_mux
>> or implementing a full wishbone interface on your carrier_sense module.
>>
>> -Ian
>>
>> On Sep 26, 2012, at 10:50 AM, Josh Blum <josh at ettus.com> wrote:
>>
>>
>> I don't understand why the compiler says the carrier_sense module would be
>> unconnected. That the registers are not connected is clear, because they
>> are connected only to my module, which is removed. I didn't change
>> anything
>> in the u2_core after I compiled the first time (when it worked). I only
>> changed the behavior description inside my carrier sense module. Undoing
>> the changes don't help. The module stays unconnected and I don't know why.
>>
>> Can anyone help me ?
>> I implemented the carrier_sense module with VHDL, because I'm a much more
>> familiar with it. I don't think that this could be a problem, could it?
>>
>>
>> I would guess its just a simple error in the code. If it helps though,
>> we use the ZPU core which is actually vhdl. I had to make this wrapper
>> block which makes sure to use std_logic only for the IOs:
>>
>> http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd
>>
>> -josh
>>
>> _______________________________________________
>> USRP-users mailing list
>> USRP-users at lists.ettus.com
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>>
>>
>
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