[USRP-users] Unable to connect module

Ian Buckley ianb at ionconcepts.com
Wed Sep 26 14:51:28 EDT 2012


Tim,
As an additional note…clearly the setting_reg's are not VHDL since they are instantiations of existing Verilog code…they are pruned because they have no connected outputs, having connected inputs will not stop pruning. In the case of sr_cs_rssi_reg and sr_cs_settings_reg this will always occur even after you solve the pruning of the carrier_sense module.
In addition, a different but related issue you haven't noticed yet…setting reg's are Write-Only, you can not use them to read values as part of the memory map…to do this you have two choices, the wb_readback_mux or implementing a full wishbone interface on your carrier_sense module.

-Ian

On Sep 26, 2012, at 10:50 AM, Josh Blum <josh at ettus.com> wrote:

> 
>> I don't understand why the compiler says the carrier_sense module would be
>> unconnected. That the registers are not connected is clear, because they
>> are connected only to my module, which is removed. I didn't change anything
>> in the u2_core after I compiled the first time (when it worked). I only
>> changed the behavior description inside my carrier sense module. Undoing
>> the changes don't help. The module stays unconnected and I don't know why.
>> 
>> Can anyone help me ?
>> I implemented the carrier_sense module with VHDL, because I'm a much more
>> familiar with it. I don't think that this could be a problem, could it?
>> 
> 
> I would guess its just a simple error in the code. If it helps though,
> we use the ZPU core which is actually vhdl. I had to make this wrapper
> block which makes sure to use std_logic only for the IOs:
> http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd
> 
> -josh
> 
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