[USRP-users] Unable to connect module

Tim Schuschies tim.schuschies at googlemail.com
Wed Sep 26 07:46:06 EDT 2012


Hi All,
I ask this question yesterday already, but I sadly didn't get an answer.
I'm normally not impatient, but I'd like to go on with my design. In
addition I have some more information for my problem.
I implemented a VHDL-module as a submodule of "u2_core". My module is
called "carrier_sense". I connected it to ddc_chain0 via the wires
"sample_rx0" and "strobe_rx0". I also connected it with 3 registers of
settings bus. My implementation in u2_core.v looks like this:

wire[31:0] cs_settings,cs_rssi,cs_status;
carrier_sense carrier_sense0
( .sample_in(sample_rx0),.clk(dsp_clk),.rst(dsp_rst),.strobe(strobe_rx0),
  .settings(cs_settings),.rssi_o(cs_rssi),.status_o(cs_status));
// Registers
setting_reg # (.my_addr(SR_CARRIER_SENSE+0)) sr_cs_rssi_reg
(.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(cs_rssi),.out(),.changed());
setting_reg # (.my_addr(SR_CARRIER_SENSE+1)) sr_cs_status_reg
(.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(cs_settings),.changed());
setting_reg # (.my_addr(SR_CARRIER_SENSE+2)) sr_cs_settings_reg

  (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(cs_status),.out(),.changed());

The first time I compiled it without any problem. The module was included
in the design and all was nice. But after I compiled the whole design
another time, I get the following warnings from the compiler:

WARNING:Xst:1290 - Hierarchical block <carrier_sense0> is unconnected in
block <u2_core>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <sr_cs_rssi_reg> is unconnected in
block <u2_core>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <sr_cs_status_reg> is unconnected in
block <u2_core>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <sr_cs_settings_reg> is unconnected
in block <u2_core>.
   It will be removed from the design.

I don't understand why the compiler says the carrier_sense module would be
unconnected. That the registers are not connected is clear, because they
are connected only to my module, which is removed. I didn't change anything
in the u2_core after I compiled the first time (when it worked). I only
changed the behavior description inside my carrier sense module. Undoing
the changes don't help. The module stays unconnected and I don't know why.

Can anyone help me ?
I implemented the carrier_sense module with VHDL, because I'm a much more
familiar with it. I don't think that this could be a problem, could it?

Thanks to all.
Tim
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