[USRP-users] user defined outputs in custom modules

Josh Blum josh at ettus.com
Mon Sep 24 11:31:33 EDT 2012

On 09/24/2012 10:26 AM, Tim Schuschies wrote:
> 2012/9/24 Josh Blum <josh at ettus.com>
>> On 09/24/2012 08:47 AM, Tim Schuschies wrote:
>>> Hi All,
>>> I'm actually trying to implement a custom dsp rx module for USRP2 FPGA. I
>>> am using the template from Ettus and it looks like it works, but now I
>> need
>>> to send data out of the module besides the already defined signals. Is
>>> there a possibility to define an other output to such a custom module or
>>> can I somehow use the VRT to get my calculated data out?
>>> I've seen that I can use a debug output in custom modules, but how can I
>>> access these from somewhere else ?
>> I can think of two ways to help you here:
>> 1) I'm not sure about the nature of your data, but perhaps passing it
>> through UHD's streaming stuff isnt applicable for you. You can configure
>> the device to stream to a custom location, like a different udp socket
>> app running on your PC:
>> http://files.ettus.com/uhd_docs/manual/html/usrp2.html#alternative-stream-destination
>> 2) The vita standard is just an array int32s. You can register a
>> converter for the host/cpu type "s32" type. Your converter will get
>> called if you make a stream with the host/cpu type set to "sc32". You
>> can choose to do something with the buffer presented or memcpy and or
>> byteswap it into the output buffer presented:
>> http://files.ettus.com/uhd_docs/doxygen/html/namespaceuhd_1_1convert.html#a2dea5dbc00d117dfda73a726a8453f72
>> -josh
>> _______________________________________________
>> USRP-users mailing list
>> USRP-users at lists.ettus.com
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> Hi Josh,
> thanks for your quick answer, but I thinks that's not the solution for what
> I'm trying to do.
> I'm calculating the absolute value of the complex value stored in
> "ddc_out_sample" signal. The result is a 16bit value. I want to use this
> value in another module I'm also implementing in VHDL. It will be a
> submodule of u2_core.v. So I have to connect these two modules somehow. My
> question is how to connect these modules.
> In the custom_dsp_rx.v(hd) module i have 6 outputs. One of them, the debug
> output, is optional. I think I need a 7th output in that module and that's
> the problem. It seems like I have to edit the whole ddc-chain to pass my
> value through or I use the debug signal. Everything has to be implemented
> in hardware using VHDL.

Ahh, well then its probably worth breaking out of the custom dsp/framer
module stuff to push out other custom signals. You should be able to
connect your design directly into the u2p_core.v, looks for the DSP RX0


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