[USRP-users] N210 ADC & DAC sample rate

Rancid Fisch rancid.fisch at gmail.com
Wed Sep 19 15:20:38 EDT 2012


Josh,

If the same 100 MHz clock is used to drive the ADC, DAC and FPGA DSP cores,
then the sample rate of both the ADC and the DAC will be 100 MS/s. In other
words, the DAC will not run at 400 MS/s as shown in the figure (see below)--
*please comment*.




The block diagram shows that dual ADCs and DACs are used. Presumably,
depending on the RF board, one ADC/DAC is assigned to I-data and the other
to Q-data--*please comment*.

In my application, I am using the MATLAB UHD support. You referenced the
following part of the UHD code manual:

virtual void uhd::usrp::multi_usrp::set_rx_rate<http://files.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html#a587cfb5be38a16fec532793b34fbf947>
( double  *rate*,

size_t  *chan* =
ALL_CHANS<http://files.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html#afeaca319029cb49f7041461345ab641c>

)
[pure virtual]

Set the RX sample rate.
*Parameters:* ratethe rate in Sps chanthe channel index 0 to N-1 This
confuses me even more as my understanding thus far is that the ADC sample
rate and DAC sample rates are fixed (at 100 MS/s) and that the "only"
control one has over the effective sampling rate is to adjust the
decimation and interpolation factors (in MATLAB these are definitely the
only parameters that can be adjusted).

Could someone please provide further clarity?

On Wed, Sep 19, 2012 at 6:58 PM, Josh Blum <josh at ettus.com> wrote:

>
>
> On 09/19/2012 09:06 AM, Rancid Fisch wrote:
> > Greetings USRP experts of the world,
> >
> > The block diagram (
> >
> https://www.ettus.com/content/files/06983_Ettus_N200-210_DS_Flyer_HR_1.pdf
> ),
> > shows that the sample rate of the ADC is 100 MS/s, that the sample rate
> of
> > the DAC is 400 MS/s, and that both ADC and DAC are fed with the same
> clock
> > (ADC/DAC Clock).
> >
> > Firstly, please confirm the following:
> >
> >    - the sample rate of the ADC is *fixed *at 100 MS/s
> >    - the sample rate of the DAC is *fixed *at 400 MS/s
> >    - both ADC and DAC are fed with the *same *clock (ADC/DAC Clock)
> >
>
> The same 100 MHz clock drives ADC, DAC, and all FPGA DSP cores.
>
> > Secondly, using the above (or their corrected versions) as working
> > assumptions, how does one set the decimation of the Digital
> Down-Converter
> > (DDC) and the interpolation of the Digital Up-Converter (DUC) so that
> > different sampling rates can be used?
> >
>
> It depends on what application you are using. There is a UHD API call to
> set rx/tx sample rate in Sps:
>
> http://files.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html#a587cfb5be38a16fec532793b34fbf947
>
> The gnuradio, mathworks, or labview wrappers will all have a similar
> parameter to set.
>
> > Thirdly, as you can gather, I am struggling to come to grasps with the
> > basic method of operation. Therefore, if anyone could post some sort of
> > introductory text that explains, perhaps with the use of a diagram or
> two,
> > how the sampling, clocking and sampling conversion works within the USRP,
> > then I would be very happy [?].
> >
>
> You may find this helpful:
>
> http://www.ettus.com/content/files/kb/application_note_frontends_subdevices_antenna_ports.pdf
>
> http://www.ettus.com/kb
>
> http://code.ettus.com/redmine/ettus/projects/uhd/wiki
>
> -josh
>
> _______________________________________________
> USRP-users mailing list
> USRP-users at lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>



-- 
__________
Rancid Fisch

mailto:rancid.fisch at gmail.com <rancid.fisch at gmail.com>
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