[USRP-users] N210 ADC & DAC sample rate

Josh Blum josh at ettus.com
Wed Sep 19 12:58:37 EDT 2012

On 09/19/2012 09:06 AM, Rancid Fisch wrote:
> Greetings USRP experts of the world,
> The block diagram (
> https://www.ettus.com/content/files/06983_Ettus_N200-210_DS_Flyer_HR_1.pdf),
> shows that the sample rate of the ADC is 100 MS/s, that the sample rate of
> the DAC is 400 MS/s, and that both ADC and DAC are fed with the same clock
> (ADC/DAC Clock).
> Firstly, please confirm the following:
>    - the sample rate of the ADC is *fixed *at 100 MS/s
>    - the sample rate of the DAC is *fixed *at 400 MS/s
>    - both ADC and DAC are fed with the *same *clock (ADC/DAC Clock)

The same 100 MHz clock drives ADC, DAC, and all FPGA DSP cores.

> Secondly, using the above (or their corrected versions) as working
> assumptions, how does one set the decimation of the Digital Down-Converter
> (DDC) and the interpolation of the Digital Up-Converter (DUC) so that
> different sampling rates can be used?

It depends on what application you are using. There is a UHD API call to
set rx/tx sample rate in Sps:

The gnuradio, mathworks, or labview wrappers will all have a similar
parameter to set.

> Thirdly, as you can gather, I am struggling to come to grasps with the
> basic method of operation. Therefore, if anyone could post some sort of
> introductory text that explains, perhaps with the use of a diagram or two,
> how the sampling, clocking and sampling conversion works within the USRP,
> then I would be very happy [?].

You may find this helpful:




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