[USRP-users] N210 ADC & DAC sample rate

Rancid Fisch rancid.fisch at gmail.com
Wed Sep 19 09:06:33 EDT 2012


Greetings USRP experts of the world,

The block diagram (
https://www.ettus.com/content/files/06983_Ettus_N200-210_DS_Flyer_HR_1.pdf),
shows that the sample rate of the ADC is 100 MS/s, that the sample rate of
the DAC is 400 MS/s, and that both ADC and DAC are fed with the same clock
(ADC/DAC Clock).

Firstly, please confirm the following:

   - the sample rate of the ADC is *fixed *at 100 MS/s
   - the sample rate of the DAC is *fixed *at 400 MS/s
   - both ADC and DAC are fed with the *same *clock (ADC/DAC Clock)

Secondly, using the above (or their corrected versions) as working
assumptions, how does one set the decimation of the Digital Down-Converter
(DDC) and the interpolation of the Digital Up-Converter (DUC) so that
different sampling rates can be used?

Thirdly, as you can gather, I am struggling to come to grasps with the
basic method of operation. Therefore, if anyone could post some sort of
introductory text that explains, perhaps with the use of a diagram or two,
how the sampling, clocking and sampling conversion works within the USRP,
then I would be very happy [?].

Thanks.

-- 
__________
Rancid Fisch

mailto:rancid.fisch at gmail.com <rancid.fisch at gmail.com>
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