[USRP-users] N210 DDC gain

Josh Blum josh at ettus.com
Wed Sep 12 05:04:27 EDT 2012



On 09/12/2012 01:32 AM, Andrew Senior wrote:
> On 11/09/12 20:10, Josh Blum wrote:
>>> It puzzles me because I would have expected the gain would be set so
>>> that a full-scale input to the ADC gives a full-scale 16-bit output,
>>> i.e. +/-32767, but at present the gain seems to be less than half that.
>>> Is this how it should be and if so, why?
>>>
>>
>> Indeed, it looks as if a bit has been lost. This should just be a
>> software fix away. This patch doubles the multiplier scalar before the
>> bits are clipped to 16. http://pastebin.com/VUCK6yzq
>>
>> I need to look into ddc_chain.v more before merging this.
> 
> Thanks for looking into this, Josh. Can I suggest you take a look at
> cordic_z24.v? I apologise if I'm barking up the wrong tree having failed
> to understand what's really going on, but it seems to me that the code
> allows some extra width for the growth due to the CORDIC algorithm but
> then divides the result by 2 at the output. Coupled with the correction
> for the CORDIC gain in host/lib/usrp/cores/rx_dsp_core_200.cpp, I
> wondered if this has something to do with it.
> 
> Andrew.
> 
> 

Hey Andrew,

It looks like I found the bug. The scale factor is 18 bits, but the
fixed point adjustment assumed 17. Whats odd is that the tx chain code
(which is a near mirror of rx) was correct. I pushed the following patch
to the maint and master branches of UHD:

http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/f969650555e1fbf87548d861e6b5126e8a641b3e/diff/host/lib/usrp/cores/rx_dsp_core_200.cpp

-Josh




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