[USRP-users] USRP N210 external FIFO bit error

Zhou Yu-ze leonzyz at gmail.com
Sat Sep 1 12:16:21 EDT 2012

first ,thank you very much for your help!

> Zhou, You are correct, I completely miss-interpreted what you implied by
> "changing the sample rate to 30.72"
> So you have then only touched the signal processing logic in the N2x0
> database and retained the standard 50/100 MHz clock rate to all protocol
> logic?
just as you said, I didn't change the clock rate, it's still 100MHz for the
whole FPGA system.

> When you say "so the FIFO's read/write frequency is faster"..you mean only
> that there are more active operations to the Ext SRAM due to the higher
> bandwidth, not that the clock frequency is faster?
yes,just like you said.

> That indeed is a little strange then. The FIFO logic is designed so that a
> register is placed on every signal in and out on this interface and all
> these registers should be placed by the default ISE configuration supplied,
> in the IOBUF's so that timing between runs of ISE is extremely
> deterministic even without explicit timing constraints for these pins.
I believe the FIFO logic is ok . I had turn on the "keep hierarchy" option
of ISE synthesizer in order to use the chipscope to probe the signals. When
I turn off that option, and remove the  chipscope modules and reimplement
the project,download  and test, the seqnum error problem dosen't occur
I think that may because I had use a lot of resources of FPGA( especially
BRAM),while makes it difficult for ISE to place and route,turn off the keep
hierarchy option may be good for ISE to place& route,so the problem dosen't
occur. So if there are some way to constraint the strategies of place &
route,that problem can be avoid,do you think so?
But I don't know how to do that ,so can you introduce me some methods of
constraint the place& route? or other ways that can achieve the result I

> Double check that these registers are indeed placed in the I/O and that no
> slew and drive options in the UCF file have been changed, and if you could
> post a copy of your .twr file after a build that might be helpful. Also can
> you describe where you probed in the hierarchy with chipscope to determine
> that error was external to the FPGA?
Acording to the source code, the data transmitted inside  FPGA in 36bit
,the 33rd bit indicate the SOF ,so when the 33rd bit is high ,the 1st to
32nd bit indicate seqnum,so I use the 33rd bit signal as a filter ,to check
whether the bits out from external FIFO and into external FIFO are the same
with the error seqnum detected in deframer module.I mainly observe the
RAM_D_po signal in ext_fifo module as the input of external SDRAM, and the
data_in signal in ext_fifo/nobl_fifo/nobl_if as the output of external

> I always recommend that when using chipscope to only probe signals that
> are already on the internal side of I/O registers and to included extra
> pipelining on the data going to the chipscope logic to provide more
> opportunity for ISE to place this logic anywhere in the FPGA with minimal
> disturbance to the timing of the function design.
I have heard about that chipscope may affact the performance several times,
I think you're right

> Out of curiosity how are you handling the Rx data since you are running
> with a nominal 30.72 sample rate? Are you using only 8bit samples so that
> there is adequate ethernet bandwidth?
no,I use 32bit I/Q data, but each recv/send burst lasts just about half
time of the period , so the average data speed is less than gigabit

I will focus on study how to make the place&route result more like the one
I want, but I have no expierence on that ,It seems like developing FPGA
project is more than just write verilog code,
I hope I can get some seggustion for you, thank you again.
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