[USRP-users] USRP N210 external FIFO bit error

Ian Buckley ianb at ionconcepts.com
Sat Sep 1 04:10:18 EDT 2012

On Aug 29, 2012, at 5:01 AM, Zhou Yu-ze wrote:
> 2)perhaps I didn't explain my problem clearly. I said I change the sample rate to
> 30.72Msps, but I didn't change the clock of FPGA, the clock is still 100MHz,I just
> use decimation/interpolation filter to "transform" the sample rate.So it's not easy
> to get a clock of 30.72MHz from a clock of 100MHz. Beside, I don't know how to 
> modify the timestamp mechanism if I change the clock frequency of FPGA.

Zhou, You are correct, I completely miss-interpreted what you implied by "changing the sample rate to 30.72"
So you have then only touched the signal processing logic in the N2x0 database and retained the standard 50/100 MHz clock rate to all protocol logic?
When you say "so the FIFO's read/write frequency is faster"..you mean only that there are more active operations to the Ext SRAM due to the higher bandwidth, not that the clock frequency is faster?

That indeed is a little strange then. The FIFO logic is designed so that a register is placed on every signal in and out on this interface and all these registers should be placed by the default ISE configuration supplied, in the IOBUF's so that timing between runs of ISE is extremely deterministic even without explicit timing constraints for these pins. Double check that these registers are indeed placed in the I/O and that no slew and drive options in the UCF file have been changed, and if you could post a copy of your .twr file after a build that might be helpful. Also can you describe where you probed in the hierarchy with chipscope to determine that error was external to the FPGA? I always recommend that when using chipscope to only probe signals that are already on the internal side of I/O registers and to included extra pipelining on the data going to the chipscope logic to provide more opportunity for ISE to place this logic anywhere in the FPGA with minimal disturbance to the timing of the function design.

Out of curiosity how are you handling the Rx data since you are running with a nominal 30.72 sample rate? Are you using only 8bit samples so that there is adequate ethernet bandwidth?


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