[USRP-users] N210 USRP FPGA Programming

Ian Buckley ianb at ionconcepts.com
Thu Jun 14 15:25:09 EDT 2012

A quick follow up. I discussed this very briefly this AM with Josh. There are no direct references to these registers in the current ZPU firmware because they are only accessed from UHD on the host in production.  I glanced at that code quickly:

uhd/host/lib/usrp/usrp2/usrp2_regs.hpp contains a base address for them: #define SR_GPIO     184
uhd/host/lib/usrp/dboard_iface.cpp defines some methods to access them.



You are probably in luck on this one, it sounds like you just need to bit-bang those pins with firmware for your application, and all the H/W hooks exist to do this already.
The relevant firmware calls are (should be) hal_gpio_* and you can find them in firmware/zpu/lib/hal* though I don't see the definitions in my tree...nor any references to the registers in memory_map.h...perhaps Josh/John/etc can comment on that.

In H/W there are 5 registers that control these pins on the daughter board RX and TX connectors, the verilog is in gpio_atr.v.
Very briefly it works as follows: One 32bit register controls the direction of each of the 32 signals, 1 control bit per signal. The other 4 32bit registers establish the values of every signal set to an output (inputs would just be "don't care") for 4 different H/W states,
IDLE, TX, RX and FULL DUPLEX. This means that the daughter board antenna switches are controlled by hardware state changes, rather than "real time" firmware. Thus if you want to drive values to the GPIO, independent of these H/W states, read-modify-write the same bits in all 4 registers.

I'll assume you can work out the rest from here out by looking at the code. You may have to write your own HAL support, but it shouldn't be hard. One note of caution: On some daughter boards possibly writing the wrong values to these registers might cause the TX to drive the RX in the radio at damaging power level's..look at the schematics and your code carefully!


On Jun 13, 2012, at 4:22 PM, Samuel Ibarra wrote:

> Hello Ian,
> Thank you for your response. I want to be able to control pins 5, 7, 9,... , and 35 on the J401 component on the N210 (Pins G4, F5, H6, ..., and K6 on the FPGA). From the Basic_Tx/Rx daughterbaord schematic, I was able to see that some of these pins are not really used on the daughterboard. I am working on implementing a MAC protocol that will be using a number directional antennas to send our information. I wanted to use these pins in order to select the antenna direction needed for the communication. Is something like this possible? Thank you for your time and help.
> Sam
> On Wed, Jun 13, 2012 at 3:09 PM, Ian Buckley <ianb at ionconcepts.com> wrote:
> Sam,
> If you can expand on what pins exactly and perhaps your broad goals then I can give you a much better answer than something broad and generic.
> -Ian
> On Jun 13, 2012, at 2:58 PM, Samuel Ibarra wrote:
> > Hello
> > I am currently working on the USRP N210. I am trying to modify the Verilog code for the FPGA in order to gain acccess to some of the pins. I have started to go over some of the source code provided in the uhd folder, but I am unsure of how to do this. I was wondering if anyone had any advice on how to do this? I would greatly appreciate any help. Thank you.
> > Sam
> > _______________________________________________
> > USRP-users mailing list
> > USRP-users at lists.ettus.com
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

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