[USRP-users] FPGA code about IQ balance
sonywdm at 126.com
Wed Jun 6 04:54:32 EDT 2012
Thank you very much for the reply.
Besides FPGA, I also noticed in host\utils there are c++ codes such as uhd_cal_rx_iq_balance.cpp, uhd_cal_tx_iq_balance.cpp and so on. So what is the relationship between them? Do the c++ files represent something like the upper layer API and when used they call the bottom layer FPGA codes? If so, when we write applications, is extra IQ balance codes in c++ or python necessary besides FPGA?
At 2012-06-06 05:49:40,"Matt Ettus" <matt at ettus.com> wrote:
The USRP1 really doesn't have enough FPGA resources to do the corrections which we do in the newer devices. With some programming, you can do some gain correction (but not phase correction) in the AD9862 codec chip, or under some circumstances, you can do the correction on the host.
On Tue, Jun 5, 2012 at 7:37 AM, 吴达旻 <sonywdm at 126.com> wrote:
In fpga/usrp2/sdr_lib/, there is tx_frontend.v, rx_frontend.v, rx_dcoffset.v, which are to deal with the problems of dc offset and IQ balance. While in fpga/usrp1/sdr_lib/, there are not tx_frontend.v or rx_frontend.v, and rx_dcoffset.v is different with that in usrp2 codes.
Does that mean usrp1 does not deal with the problem of dc offset and IQ balance or deal with them in a simpler way? What cause this difference between usrp1 and usrp2? I wonder if in usrp1 dc offset and IQ balance are dealt with in the codes of c++ and python.
Any of your replies will be very appreciated.
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