[USRP-users] N210 Rev4 SBX with 0.3.4 code
nick at ettus.com
Wed Feb 29 13:33:59 EST 2012
On Wed, Feb 29, 2012 at 10:12 AM, steam2009 at t-online.de <
steam2009 at t-online.de> wrote:
> Hi Josh,
> yes, I'm using sc16. Would you be so kind and upload an fpga image?
It's even harder to debug the problem if you aren't using release images.
Stick to the latest master image and that will help us. It is not necessary
for the git hashes of the FPGA build to match the UHD version, only that
the FPGA compatibility number is correct. Using the FPGA image Josh linked
is the best option.
> At some point in the past I was able to successfully build one on windows
> with the ISE 13.4 but that was a freak accident I was not able to
> reproduce yet.
> Is it known if 13.4 does produce working images?
> All I got was noise but first thought different version might be the cause.
13.4 should work fine, although we build internally on 12.1. Please
describe your test setup: are you using a signal generator? What frequency?
What does the output look like? Can you post images of FFTs? Please post
the output of uhd_usrp_probe.
> Would it be possible to trigger automated image generation once a day
> for those of us stuck without a working xilinx env. My eval is bound to
> run out in a few days and so far I do not need to write custom fpga code
> so I rather not buy the full suite.
Again, this is unnecessary. FPGA work and UHD work are done in parallel,
but not lockstep. We use the FPGA compatibility number to match versions.
If the FPGA compat numbers match, it should work.
> Von: Josh Blum <josh at ettus.com>
> An: "steam2009 at t-online.de" <steam2009 at t-online.de>, "support at ettus.com"
> <support at ettus.com>
> Betreff: Re: [USRP-users] N210 Rev4 SBX with 0.3.4 code
> Datum: Wed, 29 Feb 2012 18:55:36 +0100
> Are you using the complex<int16> samples? I just pushed a fix to the
> master in regards to complex short sample converter on RX. -josh
> On 02/28/2012 05:44 PM, steam2009 at t-online.de wrote:
> > Hi,
> > is there anything special to take care of when using the 0.3.4 code?
> > Since I'm unable to build my own fpga images at the moment I tried
> > and the corresponding git from the 18. feb.
> > Everything loads fine but all I receive seems to be random noise.
> > that work perfectly fine with 0.3.2 with just show noise with 0.3.4.
> > No obvious errors displayed.
> > I've tried multiple different fpga images / git version of the driver
> code and
> > so far only 0.3.2 produce meaningful results for me.
> > On a related note, could you please release built FPGA images more often
> > and make sure to tag the corresponding code base on GIT.
> > This way we could compile the host side and be sure I have a recent
> matching fpga
> > image.
> > Thanks
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