[USRP-users] a question of FPGA resouce consumption

Josh Blum josh at ettus.com
Mon Feb 27 03:57:07 EST 2012



On 02/26/2012 11:14 PM, leonzyz wrote:
> Hi ,All,
> I downloaded the source code from
> https://github.com/EttusResearch/UHD-Mirror ,
> and built the fpga project ,but I find my project uses
> more resource than ettus.com's FAQ said. It says that the N210 fpga's
> resouce:
> General Logic: 63% free
> Memory: 66% free
> DSP Resources: 88% free
> but, my project's map report says:
> Logic Utilization:
> Number of Slice Flip Flops: 19,122 out of 47,744 40%
> Number of 4 input LUTs: 28,910 out of 47,744 60%
> Logic Distribution:
> Number of occupoed Slices: 18,784 ou of 23,872 78%
> 

How so? Sure, the current utilization has gone up a bit. New features
have been added on the development branch, while the FAQ is probably
based off the last release. In any case, the numbers don't seem
drastically different than listed on the FAQ.

Here are the relevant snippets from the latest N210R4 utilization. Note
that the percentages are utilization, whereas the FAQ listed free resources.

Number of Slice Flip Flops
19,666
47,744
41%

Number of DSP48As
31
126
24%

Number of RAMB16BWERs
41
126
32%

> I used the command "make -f Makefile.N210R3" to build the project .Is there
> anything (eg. synthesis options) I forgot to add that may lead to more
> resouce
> to be consumed? Or the project has really consumed so many resouces?
> 

All of the synthesis options are all specified in the makefile. So, if
the image builds and works, I suspect the utilization is accurate.

> I noticed that someone said that there are 2 dsp processing modules in
> the fpga project
> but only one used,is that true? and how many resouces can I get by
> taking out the unused
> dsp processing module?

Yes, you can remove the second RX DSP chain. See the *_core.v verilog
file in the top level project directory. Thats where the DSP is tied
into the design.

An alternative to removing the RX DSP would be to use a custom DSP
module and allow its IO to dangle so the DSP will be trimmed:
http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/README.txt#L29

-Josh




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