[USRP-users] USRP2 FPGA: how to use custom_defs

Marius Ciepluch wishinet at googlemail.com
Sun Feb 26 05:32:11 EST 2012

Hi Josh,

sorry for using the wrong mailing list.
It looks like it's straight-forward to modify the USRP2's FPGA.

Depending on whether I can implement it, I need to perform frequency
hopping at the FPGA (for timing reasons, with a fixed cyclic sequence
that is given).
So I need to add the hopping sequence directly at the custom_dsp_rx/tx.
Could you point me where the RF Frontend controls are implemented?
I think I'm going to add some documentation on the FPGA design to the
new Knowledge Base if it's on ;)


On 02/26/2012 06:30 AM, Josh Blum wrote:
> On 02/25/2012 04:58 PM, Marius Ciepluch wrote:
>> Hi!
>> I'm planing on adding CUSTOM_DEFS to the USRP2 FPGA image, that I want
>> to extend with custom Verilog modules.
>> (http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/README.txt)
>> I want to do this in a minimal invasive way, using some of the Simulink
>> Xilinx development stuff, that there is. Especially I want to keep the
>> DDC/DUC routines as they are for now, which are part of the DSP.
>> As far as I understand it a custom definition will completely substitute
>> any of the chain engines. Is there a way to be less destructive about that?
>> Also I'm looking for what the current chains exactly are: is there some
>> sort of flow-graph here. Did somebody already analyse this?
>> There are some custom FPGA builds here and there. I'd be happy if
>> someone contributed insights how to touch this without having to redo
>> everything.
> You can leave the existing DSP in-tact. Take a look at the comments in
> the custom dsp template:
> http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/usrp2/custom/custom_dsp_rx.v
> -Josh

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