[USRP-users] Fwd: USRP2 FPGA Held in Reset?

Ian Buckley ianb at ionconcepts.com
Thu Feb 23 13:25:07 EST 2012


Brian,
what have you got "rst" connected to? S1 directly via ball V15? In this case the LED's would light regardless of the presence of a clock.

You don't show a DCM in your code snippit...these can be temperamental sometimes at startup, a solid explicit reset is recommended after a stable input clock has been established. Why not flash a front panel LED direct from the 50 and 100MHz clocks divided down so you can see they run and also approximate the frequency (like a divide by 100,000,000 counter), I find this sanity check helpful with issues like that.

To test your card burning methodology is correct by trying to load an "off the shelf" Ettus image+firmware, that way you know you got your commands and devices correct.

I'm curious your top level is called "u2_top" not "u2_rev3".....what's the origin of your starting point RTL that you have modified?

How much of the Ettus clocking/reset/firmware load logic is reused unchanged?

Happy to help more if you are still stuck and can share more code, the devil *will* be in the fine details!

-Ian

On Feb 23, 2012, at 7:12 AM, Brian Heilig wrote:

> Dear list,
> 
> I'm using a USRP2 and have developed my own firmware and software image. Up until this point I've been using the JTAG to program the FPGA, and the UART to write my software program to the on-chip RAM. This helped me develop much faster.
> 
> Now that I'm closer to 'production' I wanted to start using the CPLD and SD card. I ran into a strange problem where it looks like the FPGA is being held in reset when I program it using the SD card. I have an FPGA image similar to the following:
> 
> input rst_n, // This is the little pushbutton switch
> output [5:0] leds,
> output [31:0] debug,
> 
> input clk_fpga_p,
> output clk_fpga_n,
> 
> ...
> 
> IBUFGDS clk_fpga_pin (.O(clk_fpga_unbuf),.I(clk_fpga_p),.IB(clk_fpga_n));
> BUFG clk_fpga_BUF (.O(clk_fpga),.I(clk_fpga_unbuf));
> 
> assign leds = {6{~rst_n}};
> reg stuff;
> always @(posedge clk_fpga)
>   stuff <= ~stuff;
> assign debug = {32{stuff}};
> 
> When I load this image via the JTAG connector I can see the 'debug' lines toggling at 25 MHz, as expected (the fpga clock is still 50 MHz because the clock divider hasn't been set to 1 yet). When I load this via the SD card I do not see the debug lines toggling. I do however see the leds toggling if I push the switch. I also verified that the fpga_clk is there and is 50 MHz by sending it out the debug lines.
> 
> So the fpga clock is there, the image clearly loaded (as is evident by the leds toggling). But it just doesn't do anything. What am I doing wrong?
> 
> I copy the image to the SD card using the following command. Not sure if this is important:
> 
> u2_flash_tool --dev=/dev/sdb -t fpga u2_top.bin -w
> 
> Thanks,
> Brian
> 
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