[USRP-users] ADC/DAC working on different frequency
plddesigner at gmail.com
Sun Feb 19 14:23:45 EST 2012
Thanks, Ian for your fast reply!
Do the packet counters on your host Linux system show increasing packet
> error's on the interface connected to the N200? I would expect this if
> transmitted packets were truncated due to FIFO starvation, resulting in
> packet fragments on the wire that would fail CRC check at the Linux host
> NIC. (Or intervening switch)
The packet counters on my host Linux system do not show increasing packet
error's on the interface connected to the N200. So, transmited packets was
not truncated due to FIFO starvation.
Than I changed clock frequency of some DSP blocks such as: "rx_frontend",
"dsp_core_rx", part of "vita_tx_chain", "tx_frontend". Data coming from
"dsp_core_rx" to "vita_rx_chain" were synchronized with 100MHz clock
("dsp_clk" signal). Data coming from "ext_fifo" to "vita_tx_chain" were
synchronized with 40MHz clock ("lms_clk" signal).
ZPU working at 50 MHz frequency. Vita timer ("time_64bit" block) working at to
Modified FPGA source is available at github:
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