[USRP-users] Replacing DSP in N2x0
Marcus D. Leech
mleech at ripnet.com
Wed Feb 15 15:02:17 EST 2012
On 02/15/2012 02:54 PM, Wilson, Jeffery (DS-1) wrote:
> Designation: Non-SSA/Finmeccanica
> Thank you for all the info. I'm not a DSP guy myself, so I don't fully
> understand the issues, in fact it may be elsewhere in the DSP module
> than the CORDIC. We certainly need to do more testing before we start
> changing things, and simulations as you suggest may be the way to go.
> -- Jeff
I'd really like to understand what the problem is. The CORDIC itself is
a very high-quality implementation. The USRP2/N2XX series use
a 20-stage CORDIC approach, which produces very high resolution. The
output register width is such that it produces an SFDR of
96dB, which is *very* decent for a DDS/NCO of any kind.
The only issue I can think of is phase noise, which will be entirely
dependant on the phase-noise of the clock system--either internal, or
the external reference. The on-board clock is a low-phase-noise
design, and using an external reference, you can get the phase noise
lower by a significant amount, depending on the quality of the
external reference. The on-board clock is good to about 5PPM or so,
as I recall, and an external reference can usually get to you 500PPB
fairly easily--that's not directly related to phase noise, but the
higher accuracy clocks generally also have much better phase noise.
> *From:*Ian Buckley [mailto:ianb at ionconcepts.com]
> *Sent:* Tuesday, February 14, 2012 3:51 PM
> *To:* Wilson, Jeffery (DS-1)
> *Cc:* usrp-users at lists.ettus.com
> *Subject:* Re: [USRP-users] Replacing DSP in N2x0
> Yes, there are commercial users of the USRP H/W who have swapped some
> or all of the signal processing H/W out for something custom,
> generally because they want to do something unusual and very specific
> for their application. I'm not personally aware of anyone having done
> what you suggest (swap out the CORDIC for another DDFS
> implementation), but it would be a relatively easy task as that
> portion of the design is largely simple streaming data and an uber
> simple 32bit bus used to program the various registers that program
> the DDC frequency etc. The only consequence to the system as a whole I
> can think of off hand is that you might change the number of DSPCLK
> cycles of latency between an "off-air signal" being sampled and it
> being time stamped in the downstream vita logic, and that you might
> need to modify firmware so that the appropriate frequency value is
> programmed for your own DDC implantation.
> Perhaps as a first you should simulate the CORDIC in isolation with
> test data and compare that with a reference model and/or alternate
> DDFS implementation such as a lookup table as a first step to
> establish if your supposition is correct?
> Removal of the TX DSP is trivial, track down dsp_core_tx, it contains
> most of the TX data path and comment it out...you should probably tie
> the strobe signal passing upstream to the vita logic.
> On Feb 14, 2012, at 12:14 PM, Wilson, Jeffery (DS-1) wrote:
> I've been running some tests using an N200 (I also have an N210 at my
> disposal), and I'm a bit unhappy with the performance of the RX DSP
> (most likely the CORDIC itself). I wasn't able to find much by
> searching the list archives or the web, but I was wondering if it is
> at all common for users to swap out the UHD implementation for a
> separate and/or proprietary IP core with better characteristics. Could
> anyone point me to any examples of this (if they exist)?
> I also remember seeing something at one time about removing the whole
> TX chain to make more room on the FPGA for RX-only applications, but
> haven't been able to relocate it. I'd appreciate it if someone could
> point me to that info as well.
> Jeff Wilson
> Software Engineer
> DRS Signal Solutions, Inc.
> Direct: 301.944.8772
> USRP-users mailing list
> USRP-users at lists.ettus.com <mailto:USRP-users at lists.ettus.com>
> USRP-users mailing list
> USRP-users at lists.ettus.com
Shirleys Bay Radio Astronomy Consortium
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