[USRP-users] Curious About Phase Noise of N210
robertwatsonbath at googlemail.com
Tue Feb 14 15:12:31 EST 2012
On 14 February 2012 18:04, Ben Hilburn <ben.hilburn at ettus.com> wrote:
> If you decide to do this yourself, the quality of the external reference
> really shouldn't affect it to a large degree, so I wouldn't fuss over it too
Is it really true that the reference isn't that important?
If I understand the N210 schematics correctly the 10MHz reference
(internal or external) is applied to the AD9510 to phaselock a 100MHz
VCXO. Within the PLL bandwidth (3kHz?) the phase noise will be around
20*log10(10) (ie 20dB) worse than the reference. Outside the loop
bandwidth off the PLL the phase noise will be that of the untamed
VCXO. The 100MHz clock from the VCXO makes its way to the
daughterboard interface and, in the case of the WBX board, is used a
reference clock for the ADF4350 wideband VCO/PLL. So, depending on the
output frequency and PLL loop bandwidth the final output phase noise
will be further degraded depending on the effective frequency
multiplication factor. Basically shouldn't the phase noise of the
output will be 20*log10(N) times worse than the reference source phase
For our work the performance of the N210 is fine, the limitations lie
elsewhere, so for me at least it's a bit academic - nonetheless be
nice to know.
PS. Can't find the schematics on the new Ettus site?
More information about the USRP-users