[USRP-users] USRP-users Digest, Vol 18, Issue 6
ianb at ionconcepts.com
Wed Feb 8 13:02:12 EST 2012
I'm not seeing an immediate problem on the ethernet transmit side near the MAC..the FIFO's running on the dsp clock (100->40MHz) are all 32bits wide and so should sustain the 125MB/S requirement of the MAC. However I've never delved in the packet router RTL and there might be a potential bottleneck in there with running the clock at 40% of the original.
On the receive side I do see a potential problem, when I designed the FIFO in the external SRAM my throughput calculations assumed the RAM was clocked at 100MHz and there is no padding...this FIFO can only sustain throughput of dspclk/2 * 2bytes = 40MB/s in your case, though it can burst twice that. Streaming at decimation 4/5/6/7/8/9 would never work.
Do the packet counters on your host Linux system show increasing packet error's on the interface connected to the N200? I would expect this if transmitted packets were truncated due to FIFO starvation, resulting in packet fragments on the wire that would fail CRC check at the Linux host NIC. (Or intervening switch)
On Feb 7, 2012, at 3:59 AM, Карпенков Андрей Сергеевич wrote:
> Hello list,
> I decrease system clock frequency of N200 from 100 MHz to 40 MHz. All blocks of FPGA project work correctly (debug uart, leds), but Ethernet does not work. ZPU correctly receive and transmit packets (debug swithed on in the ZPU firmware), but PC does not see them. It seems like Ethernet MAC does not have time to send packets to PC. Any idea why so happend? Looking forward for your advise on this issue. May be somewhere need to place FIFO buffer?
> Andrew Karpenkov
> USRP-users mailing list
> USRP-users at lists.ettus.com
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