[USRP-users] USRP-users Digest, Vol 18, Issue 6

Карпенков Андрей Сергеевич plddesigner at gmail.com
Tue Feb 7 06:59:42 EST 2012


Hello list,

I decrease system clock frequency of N200 from 100 MHz to 40 MHz. All
blocks of FPGA project work correctly (debug uart, leds), but Ethernet does
not work. ZPU correctly receive and transmit packets (debug swithed on in
the ZPU firmware), but PC does not see them. It seems like Ethernet MAC
does not have time to send packets to PC. Any idea why so happend? Looking
forward for your advise on this issue. May be somewhere need to place FIFO
buffer?

Thanks!

Regards,
Andrew Karpenkov
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