[USRP-users] [Discuss-gnuradio] How to use USRP N210 UHD
nick at ettus.com
Thu Feb 2 15:24:49 EST 2012
OK, thanks for the update. Sometimes it takes a while for messages to get
through on the discuss-gnuradio list. Sorry for the snippy reply.
I don't know that anyone has simulated the entire N210 FPGA. What testbench
are you using for the top-level simulation? There's a USRP2 testbench in
fpga/usrp2/testbench, but it hasn't been updated in a while and there isn't
a corresponding testbench for the current N210 FPGA code.
CC'ing usrp-users to put this on the right list.
On Thu, Feb 2, 2012 at 12:13 PM, FARHAN BABAR <flakon01 at gmail.com> wrote:
> First of all your discussion forum have some problem its says resend your
> message that's why I by mistake send you 3 time message sorry for that
> the problem i am facing i am window user. .help on internet is just for
> Linux users. i just took
> "EttusResearch-UHD-Mirror-release_003_003_001-197-ge30cf4e" this zip folder
> from your webiste.
> and make a project in Xilinx 13.1. project is compiling fine. . but in
> simulation some bootrams are empty, ADC model is not giving me any output.
> i just want to test your this design and modify it for MIMO project
> On 2 February 2012 21:59, Nick Foster <nick at ettus.com> wrote:
>> OK so repeating your question three times is not going to help you get an
>> answer. For starters, ask on the right list -- this question belongs on
>> usrp-users, not on discuss-gnuradio, since it's USRP-specific.
>> Second, what exactly is the problem you're having? "Not running
>> properly" is so vague as to cover everything from incorrect setup to an
>> infestation of bees. Please provide the error messages or output you're
>> seeing, vs. what you're expecting.
>> On Thu, Feb 2, 2012 at 11:56 AM, farhanbabar <flakon01 at gmail.com> wrote:
>>> I am newbie to USRP (N210) i want to modify its FPGA core for timing
>>> synchronization of MIMO as project.
>>> I downloaded "EttusResearch-UHD-Mirror-release_003_003_001-197-ge30cf4e"
>>> this and using xilinx 13.1 in window XP. . but my simulation is not
>>> properly i just made project and add required file to project in
>>> (top level to down each an every file which are used in any module). But
>>> simulation is not working properly test bench is also given by "Ettus". i
>>> Google it a lot but no source of information
>>> Please you guys help me from where did I start
>>> View this message in context:
>>> Sent from the GnuRadio mailing list archive at Nabble.com.
>>> Discuss-gnuradio mailing list
>>> Discuss-gnuradio at gnu.org
> Everyone Is a Genius. But if you judge a fish on its ability to climb a
> tree, it will live its whole life believing it is stupid.
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