[USRP-users] USRP2 FPGA development questions

Matthias Wilhelm wilhelm at informatik.uni-kl.de
Thu Nov 18 05:35:54 EST 2010


Am 17.11.2010 um 19:31 schrieb Matt Ettus:

> On 11/17/2010 10:05 AM, Marc Epard wrote:
>> We're experimenting with changes to the USRP2's FPGA. We started with
>> the UHD code and successfully built the same image downloadable from
>> Ettus, but Xilinx ISE 12.2 reports thousands of warnings and some
>> time constraint violations. This is only my second Verilog project
>> (my background is in software development) and I have a few
>> questions.
>> 
>> How do you guys manage the warnings? Software development experience
>> has conditioned me to treat warning as errors and eliminate each one.
>> This doesn't appear to be possible with the Xilinx tools. The
>> Filtering feature seems barely useful in that you can't cleanly
>> isolate files or modules. Is there something I'm missing?
> 
> Unfortunately, it is essentially impossible to get rid of warnings in Xilinx tools.  The best you can hope for is to grep for the ones you care about.
> 
>> When do you take time constraint violations seriously? How do I know
>> when my changes have caused a real timing problem?
> 
> Yes, very seriously.  You shouldn't see timing violations.  Which branch are you using, and how exactly are you doing the compile?
> 
> Matt

We have been doing some work on USRP2's FGPA, I think ISE always complained about timing for me, but it works anyway (mostly?). 

With ISE 12.2 and the newest git revision of the vanilla fpga code in the UHD repository, I get for "make -f Makefile.udp bin":
> ............
> 
> **************************
> Generating Clock Report
> **************************
> 
> +---------------------+--------------+------+------+------------+-------------+
> |        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
> +---------------------+--------------+------+------+------------+-------------+
> |      ser_rx_clk_buf |      BUFGMUX3| No   |  206 |  0.348     |  1.085      |
> +---------------------+--------------+------+------+------------+-------------+
> |u2_core/buffer_pool/ |              |      |      |            |             |
> |            wb_clk_i |      BUFGMUX4| No   | 2639 |  0.686     |  1.373      |
> +---------------------+--------------+------+------+------------+-------------+
> |    clk_to_mac_BUFGP |      BUFGMUX0| No   |  216 |  0.382     |  1.120      |
> +---------------------+--------------+------+------+------------+-------------+
> |u2_core/rx_eth_fifo/ |              |      |      |            |             |
> |     middle_fifo/clk |      BUFGMUX7| No   | 6482 |  0.630     |  1.316      |
> +---------------------+--------------+------+------+------------+-------------+
> |   GMII_RX_CLK_BUFGP |      BUFGMUX1| No   |  213 |  0.410     |  1.144      |
> +---------------------+--------------+------+------+------------+-------------+
> |     ser_tx_clk_OBUF |      BUFGMUX6| No   |    6 |  0.046     |  0.905      |
> +---------------------+--------------+------+------+------------+-------------+
> 
> * Net Skew is the difference between the minimum and maximum routing
> only delays for the net. Note this is different from Clock Skew which
> is reported in TRCE timing report. Clock Skew is the difference between
> the minimum and maximum path delays which includes logic delays.
> 
> Timing Score: 6149 (Setup: 6149, Hold: 0, Component Switching Limit: 0)
> 
> WARNING:Par:468 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in
>    your design.
> 
>    Review the timing report using Timing Analyzer (In ISE select "Post-Place &
>    Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
> 
>    Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to
>    ensure the best options are set in the tools for timing closure.
> 
>    Use the Xilinx "SmartXplorer" script to try special combinations of
>    options known to produce very good results.
> 
>    Visit the Xilinx technical support web at http://support.xilinx.com and go to
>    either "Troubleshoot->Tech Tips->Timing & Constraints" or "
>    TechXclusives->Timing Closure" for tips and suggestions for meeting timing
>    in your design.
> 
> Number of Timing Constraints that were not applied: 1
> 
> Asterisk (*) preceding a constraint indicates it was not met.
>    This may be due to a setup or hold violation.
> 
> ----------------------------------------------------------------------------------------------------------
>   Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
>                                             |             |    Slack   | Achievable | Errors |    Score   
> ----------------------------------------------------------------------------------------------------------
> * TS_dcm_out = PERIOD TIMEGRP "dcm_out" TS_ | SETUP       |    -0.711ns|    10.711ns|      20|        4609
>   clk_fpga_p HIGH 50%                       | HOLD        |     0.459ns|            |       0|           0
> ----------------------------------------------------------------------------------------------------------
> * TS_clk_div = PERIOD TIMEGRP "clk_div" TS_ | SETUP       |    -0.592ns|    21.184ns|       8|        1540
>   clk_fpga_p * 2 HIGH 50%                   | HOLD        |     0.646ns|            |       0|           0
> ----------------------------------------------------------------------------------------------------------
>   TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_ | SETUP       |     0.039ns|     7.961ns|       0|           0
>   CLK" 8 ns HIGH 50%                        | HOLD        |     0.663ns|            |       0|           0
> ----------------------------------------------------------------------------------------------------------
>   TS_clk_to_mac = PERIOD TIMEGRP "clk_to_ma | SETUP       |     0.078ns|     7.922ns|       0|           0
>   c" 8 ns HIGH 50%                          | HOLD        |     0.691ns|            |       0|           0
> ----------------------------------------------------------------------------------------------------------
>   TS_ser_rx_clk = PERIOD TIMEGRP "ser_rx_cl | SETUP       |     0.102ns|     9.898ns|       0|           0
>   k" 10 ns HIGH 50%                         | HOLD        |     0.702ns|            |       0|           0
> ----------------------------------------------------------------------------------------------------------
>   TS_clk_div_to_dsp_clk = MAXDELAY FROM TIM | SETUP       |     0.164ns|     9.836ns|       0|           0
>   EGRP "clk_div" TO TIMEGRP "dcm_out"       |             |            |            |        |            
>      10 ns                                  |             |            |            |        |            
> ----------------------------------------------------------------------------------------------------------
>   TS_clk_fpga_p = PERIOD TIMEGRP "clk_fpga_ | SETUP       |     6.686ns|     3.314ns|       0|           0
>   p" 10 ns HIGH 50%                         | HOLD        |     0.720ns|            |       0|           0
>                                             | MINPERIOD   |     4.013ns|     5.987ns|       0|           0
> ----------------------------------------------------------------------------------------------------------
>   TS_cpld_clk = PERIOD TIMEGRP "cpld_clk" 4 | MINPERIOD   |    38.684ns|     1.316ns|       0|           0
>   0 ns HIGH 50%                             |             |            |            |        |            
> ----------------------------------------------------------------------------------------------------------
> 
> 
> Derived Constraint Report
> Review Timing Report for more details on the following derived constraints.
> To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
> or "Run Timing Analysis" from Timing Analyzer (timingan).
> Derived Constraints for TS_clk_fpga_p
> +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
> |                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
> |           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
> |                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
> +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
> |TS_clk_fpga_p                  |     10.000ns|      5.987ns|     10.711ns|            0|           28|            6|      1902815|
> | TS_dcm_out                    |     10.000ns|     10.711ns|          N/A|           20|            0|       558432|            0|
> | TS_clk_div                    |     20.000ns|     21.184ns|          N/A|            8|            0|      1344383|            0|
> +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
> 
> 2 constraints not met.
> 
> 
> Generating Pad Report.
> 
> All signals are completely routed.
> 
> WARNING:Par:283 - There are 11 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
> 
> Total REAL time to PAR completion: 7 mins 30 secs 
> Total CPU time to PAR completion: 7 mins 29 secs 
> 
> Peak Memory Usage:  786 MB
> 
> Placer: Placement generated during map.
> Routing: Completed - No errors found.
> Timing: Completed - 28 errors found.
> 
> Number of error messages: 0
> Number of warning messages: 15
> Number of info messages: 1

I'm sure there is more info buried in the floor of warnings. 

Are there some parameters to tweak to get it right?

Matthias



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