[USRP-users] USRP2 FPGA development questions
mepard at me.com
Wed Nov 17 13:05:05 EST 2010
We're experimenting with changes to the USRP2's FPGA. We started with the UHD code and successfully built the same image downloadable from Ettus, but Xilinx ISE 12.2 reports thousands of warnings and some time constraint violations. This is only my second Verilog project (my background is in software development) and I have a few questions.
How do you guys manage the warnings? Software development experience has conditioned me to treat warning as errors and eliminate each one. This doesn't appear to be possible with the Xilinx tools. The Filtering feature seems barely useful in that you can't cleanly isolate files or modules. Is there something I'm missing?
When do you take time constraint violations seriously? How do I know when my changes have caused a real timing problem?
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